Mixed Signal Design Engineer
Limerick, Munster, Ireland
As a Mixed Signal Design Engineer, you will be responsible for designing and developing mixed-signal integrated circuits, including …
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Limerick, Munster, Ireland
As a Mixed Signal Design Engineer, you will be responsible for designing and developing mixed-signal integrated circuits, including …
Santa Clara, California, United States
As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading chips. We are …
Durham, North Carolina, United States
As a Digital Design Engineer, you will contribute to the design, development, and verification of digital integrated circuits …
Singapore-Yishun
Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design …
Office - USA - CA - Headquarters
… and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design …
Armenia
… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design …
San Jose, California, United States +1 location
Pay posted by employer$86,043–$118,309
As a Digital Design Engineer, you will contribute to the design, development, and verification of digital integrated circuits …
Santa Clara, California, United States
… on the world. NVIDIA is looking for sharp, curious, and motivated students who are passionate about formal verification, digital design, and computer architecture. In this role, you will help verify advanced processor and …
Bengaluru, Karnataka, India
… BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools. Hands on experience in DFT verification using Gate Level Simulations with timing annotations. Hands on experience in solving DFT problems, …
Bengaluru, Karnataka, India
Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. …
Bengaluru, Karnataka, India
Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. …
Santa Clara, California, United States +2 locations
We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard …
Fort Collins, Colorado, United States
Pay posted by employer$61,900–$99,000 USD per year
ASIC Design Automation Engineer Broadcom’s ASIC Products Division is seeking a Design Automation Software Development …
Bengaluru, Karnataka, India
The Role and Impact: As a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly …
Wilmington, Massachusetts, United States
Pay posted by employer$87,188–$119,906
… innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . Product Engineer Analog Devices Inc. is seeking an intelligent new graduate as Product (Design Evaluation) Engineer to join …
Bengaluru, Karnataka, India +1 location
… [ Implement ECOs : Generate and execute functional and timing Engineering Change Orders (ECOs) late in the design cycle. Conduct Sign-Off Analysis : Perform Logical Equivalence Checking (LEC), parasitic extraction, Static …
Santa Clara, California, United States +5 locations
… problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position …
Hillsboro, Oregon, United States
Pay posted by employer$164,470–$232,190 USD per year
Position Overview As a Platform Hardware Design Engineer, you will drive the end-to-end development of platform hardware, translating high-level system …
Bengaluru, Karnataka, India
… 16nm, 7nm, 5nm, 4nm). Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets. Define and refine hierarchical PNR strategies, IO …
CLOSED-India, Bangalore, Aveda Meta
… 16nm, 7nm, 5nm, 4nm). Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets. Define and refine hierarchical PNR strategies, IO …
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