CPU Physical Design Engineer · AnywhereEditFilters
173 matching jobs for “CPU Physical Design Engineer”
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Pay posted by employer$122,440–$200,340 USD per year
… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …
Pay posted by employer$122,440–$200,340 USD per year
… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …
… functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements. Defines and develops scalable and reusable IP verification plans, …
Role Summary We are seeking a Senior Hardware Design Engineer to join our Product HW design team , working on advanced networking systems where signal …
Santa Clara, California, United States +2 locations
Pay posted by employer$122,440–$232,190 USD per year
… functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements. Defines and develops scalable and reusable IP verification plans, …
Santa Clara, California, United States +2 locations
Pay posted by employer$141,910–$232,190 USD per year
… functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements. Defines and develops scalable and reusable IP verification plans, …
Santa Clara, California, United States +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
Santa Clara, California, United States +1 location
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique …
… definition, RTL development, synthesis, timing closure, DFT collaboration, and close partnership with physical design teams to deliver robust, production‑ready designs. Key Responsibilities: Define and develop …
Santa Clara, California, United States +4 locations
Pay posted by employer$220,920–$311,890 USD per year
… deliver power, performance, and scalability across future nodes and products. We're looking for a Principal Engineer who thrives on solving hard problems, someone who can bring deep circuit expertise and help define the …
Santa Clara, California, United States +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
Pay posted by employer$122,440–$172,860 USD per year
… leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for …
… work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As …
… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …
… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …
… want hands-on experience designing and bringing new technology to life? As a GPU & AI Accelerator Hardware Design Undergraduate Intern , you will work alongside experienced engineers developing next-generation GPU and AI …
… Use perf, Valgrind (Memcheck, Massif, Helgrind), and kernel utilities to profile OS memory and CPU management, eliminate memory leaks, resolve race conditions, and minimize CPU bottlenecks. Wireless Stack & …