1,000+ matching jobs for “Engineer, Sr. Process Design”

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Intel

Senior CPU Circuit Design Engineer

Malaysia, Penang

The Role and Impact As a Senior CPU Circuit Design Engineer, you will play a pivotal role in designing and developing custom digital circuits for CPUs, …

Added Oct 27, 2026

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Stryker

Senior Design Engineer, R&D

Carrigtwohill, Ireland

… activities, ensuring timely closure and effective risk mitigation Assess product risks and implement design or process improvements to enhance safety and reliability Design & Change Leadership Drive design …

Added Oct 27, 2026

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Venture Global

Lead Engineer, Process

Houston, Texas, United States

Full time
Regular

Process MOC/HAZOP signoff Site process technical authority Maintains / responsible for master P&ID redline register …

Added Nov 3, 2026

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Intel

GPU Senior Logic Design Engineer

Bengaluru, Karnataka, India

GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Intel

CPU Senior Clock Design Engineer

Bengaluru, Karnataka, India

The Role and Impact Join a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Senior Clock Design Engineer, you will contribute to the design, implementation, analysis, and optimization of clock …

Added Oct 27, 2026

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Intel

Senior CPU Circuit Design Engineer

Malaysia, Penang

The Role and Impact As a Senior CPU Circuit Design Engineer, you will play a pivotal role in designing and developing custom digital circuits for CPUs, …

Added Oct 27, 2026

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Marvell Technology

Senior Staff Digital Design Engineer

Irvine, California, United States +1 location

Full time
Regular

… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high …

Added Nov 3, 2026

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Nvidia

Senior Chip Design Verification Engineer

Israel, Yokneam +1 location

We are now looking for a Chip Design Verification Engineer. NVIDIA is seeking a verification engineer to join the chip design methodologies …

Added Oct 29, 2026

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Analog Devices

Senior Analog IC Design Engineer

Philippines, Bonifacio Global City

Working within an analog/mixed-signal design team based in our Valencia (Spain), Cork (Ireland), Limerick (Ireland), Newbury (England), Cavite …

Added Nov 3, 2026

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Massachusetts Mutual Life Insurance

Business Process Engineer

Springfield, Massachusetts, United States

Full time
Regular

Pay posted by employer$121,800–$159,800

Business Process Engineer Continuous Improvement Team Full-time, Springfield, MA The Opportunity As a Business Process …

Added Nov 3, 2026

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Venture Global

Principal Engineer, Process

Houston, Texas, United States

Full time
Regular

develops and maintains process engineering requirements, practices, methods, tools, and operating guidance; provides independent technical …

Added Nov 3, 2026

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Nvidia

Senior Mixed Signal Design Engineer

Santa Clara, California, United States

… frontiers of the high-speed DRAM SerDes solutions. What you'll be doing: Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces Solve challenges of circuit designs in the latest CMOS FinFET …

Added Oct 31, 2026

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Nvidia

Senior Circuit Design Engineer - Noise

Santa Clara, California, United States +1 location

We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in …

Added Oct 27, 2026

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Nvidia

Senior Mixed Signal Design Engineer

Santa Clara, California, United States

… to amplify human creativity and intelligence. We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling …

Added Oct 31, 2026

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RTX

Senior Motor Controls Design Engineer

Tucson, Arizona, United States

… Analog & Power (EAP) Team is looking for mid-career engineers who have electronics knowledge to help design robust motor control systems. The EAP Department is responsible for the development, from concept to …

Added Oct 27, 2026

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Nvidia

Senior Chip Design Verification Engineer

Beersheba, Southern District, Israel +1 location

NVIDIA is looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high …

Added Oct 27, 2026

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RTX

Senior Mechanical Design Engineer (Onsite)

Jupiter, Florida, United States

… packages using Pro-Cert methodology and data-driven decision-making to improve quality, cost, and product/process producibility. Lead Engineering First Piece Reviews at suppliers, Cost of Poor Quality and production …

Added Oct 27, 2026

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RTX

Senior Mechanical Design Engineer (Onsite)

Jupiter, Florida, United States

Added Oct 27, 2026

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RTX

Senior Power Design Electrical Engineer

Portsmouth, Rhode Island, United States

… the future of aerospace and defense. The Raytheon Hardware Engineering Organization leads the hardware design, development and production support of a wide breadth of air, land, sea, and space systems. The Hardware …

Added Oct 27, 2026

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Intel

Senior DFT Logic Design Engineer

Phoenix, Arizona, United States +2 locations

Pay posted by employer$141,910–$269,100 USD per year

… foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and …

Added Oct 27, 2026

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Intel

Senior DFT Logic Design Engineer

Phoenix, Arizona, United States +2 more

Pay posted by employer$141,910–$269,100 USD per year

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Qualifications · employer excerpt

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or…

About this opportunity

Original employer description

Job Details:

Job Description:

About the Group

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Intel Foundry will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IP's. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. Come join us and do something wonderful.

The Aerospace, Defense, Government (ADG) - The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, DFT/DFM insertion, ATPG validation methodology and flows.

The successful candidate will:

Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
Create content, application notes and deliver technical training/presentations.
Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level.
Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Core Competencies

Customer-oriented attitude and mindset.
Self-driven and results-oriented, capable of effectively working multiple tasks.
Team player - effective team-work skillset to drive and find solutions for customer design implementation issues/challenges.
Analytical problem-solving skills.
Effective communication skills, as well as experience in collaboration, listening and providing feedback.

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

US Citizenship required.
Ability to obtain a US Government Security Clearance.
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
3+ years of experience with advanced CMOS processes (16nm and below).
3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, ...) at ASIC design block level and at full chip level. Performing ATPG validation and DFT timing and DFT signoff at SOC level.
4+ years of experience in one or more of the following scripting languages e.g. Python, Perl, Tcl, and/or shell scripting.

Preferred Qualifications

Active US Government Security Clearance with a minimum of Secret level.
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
Hands-on experience in one or more areas of Design Implementation and methodology - (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability, etc).
Experience using major EDA tools suites for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die design.
Experience in building/developing quality DFT/DFX insertion flow and ATPG validation flow.
Experience in working with RTL and Hard IP designers on DFT/DFM implementation methodology.
Experience in working with physical designers on DFT/DFM physical implementation, validation, and DFT timing signoff.
Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
Customer facing experience.
Semiconductor foundry experience.

What We Offer

Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
Direct customer engagement and technical leadership in advanced semiconductor design
Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
Competitive compensation
Professional development in DFT methodologies and foundry services
Direct impact on national security through advanced semiconductor technology solutions

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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