1,000+ matching jobs for “Physical Design Engineer”

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Broadcom

ASIC Design - Floorplan Engineer

Fort Collins, Colorado, United States

Full time
Regular

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …

Added Oct 31, 2026

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KLA

Sr. Systems Design Engineer

Milpitas, California, United States 2 postings

Full time
Regular

Pay posted by employer$159,500–$271,200 per year

… devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA’s metrology and inspection …

Added Oct 15, 2026

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Broadcom

I/O Design Engineer

Chandler, Arizona, United States

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design …

Added Oct 5, 2026

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Intel

EDA Design Automation Engineer

Malaysia, Penang

The Role and Impact Join Intel as an EDA Tools Hardware Engineer, where you will play a pivotal role in advancing hardware design tools, flows, and methodologies. In this …

Added Oct 27, 2026

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Intel

Quantum Qubit Design Engineer

Hillsboro, Oregon, United States +7 locations

Pay posted by employer$141,910–$269,100 USD per year

… approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum …

Added Oct 27, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

GPU Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Boeing

Associate Structural Design Engineer

USA - North Charleston, SC

In person

Pay posted by employer$85,000–$115,000

… integrating and documenting primary and secondary structural requirements to establish the system design Develops, maintains and modifies basic structural and interior payload system and component designs, using …

Added Oct 12, 2026

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Intel

Platform Hardware Design Engineer

Hillsboro, Oregon, United States

Pay posted by employer$164,470–$232,190 USD per year

Position Overview As a Platform Hardware Design Engineer, you will drive the end-to-end development of platform hardware, translating high-level system …

Added Oct 27, 2026

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Intel

GPU Design Verification Engineer

Folsom, California, United States +1 location

Pay posted by employer$122,440–$200,340 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Oct 28, 2026

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Cisco Systems

ASIC Design Verification Engineer

Taipei, Taiwan, Taiwan

… ASICs more general and programmable. Cisco Common ASIC Group is looking for an expert Senior Verification Engineer to drive existing projects and engage in new development of our next generation switching systems. As part …

Added Oct 27, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

The Role and Impact: As a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly …

Added Oct 27, 2026

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Broadcom

Memory Layout Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

… Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture. Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes. Extensive …

Added Oct 5, 2026

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Intel

Senior Design Verification Engineer

Santa Clara, California, United States

Pay posted by employer$164,470–$311,890 USD per year

About the Role Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of …

Added Oct 27, 2026

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Nvidia

Senior Thermal Design Engineer

Santa Clara, California, United States

We are looking for a highly motivated Senior Thermal Product Design Engineer to join this dynamic and innovative team to support the next generation of products and thermal …

Added Oct 27, 2026

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Intel

Chassis IP Design Engineer

Bengaluru, Karnataka, India

The Role and Impact As an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP …

Added Oct 27, 2026

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Intel

Analog Circuit Design Engineer

Bengaluru, Karnataka, India

Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced …

Added Oct 27, 2026

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Cisco Systems

Senior Design Verification Engineer

Belgrade, Central Serbia, Serbia

… stages, from architectural discussions to emulation and simulation support. Collaborate with global teams, design and block owners, chiplet and full-chip owners as well as emulation, compiler, and software development …

Added Oct 27, 2026

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Senior ASIC Design Engineer

Vancouver, Washington, United States

Full time
Reg Employee

Pay posted by employer$116,150–$182,400 USD per year

Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification. …

Added Oct 12, 2026

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Intel

SoC Design Verification Engineer

Bengaluru, Karnataka, India 2 postings

… the future of computing and enable groundbreaking advancements in the industry. Position Overview: As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) …

Added Oct 27, 2026

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Intel

SoC Design Verification Engineer

Bengaluru, Karnataka, India

Added Oct 27, 2026

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Intel

Quantum Qubit Design Engineer

Hillsboro, Oregon, United States +7 more

Pay posted by employer$141,910–$269,100 USD per year

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Qualifications · employer excerpt

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.…
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits |…

About this opportunity

Original employer description

Job Details:

Job Description:

Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey Key Responsibilities • Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules • Architect qubit and readout element standard cell design and automation • Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability • Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology • Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors • Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts • Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors • Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs • Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk • Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors • Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI • Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff • Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Qubit processor to ASIC control • Designing and taping out electrical characterization test structures to characterize qubit and interconnect performance and yield • Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable thermal analysis of large scale quantum processors • Implement PDK collateral into customized design environments and create and maintain customized design workflows for qubit processors • Working with external customers to understand their needs and provide solutions based on Intel's quantum PDK • Ensure successful implementation of Intel quantum PDK design collateral and EDA tool capabilities for External Customers • Ensuring external customer designs are successfully taped out with silcon run to end-of-line on schedule As a successful candidate, you must possess • Excellent communication and presentation skills for technical and non-technical audiences • Keen experimental insight with the ability to design and focus on practical implementations • High motivation and enthusiasm for self-directed, hands-on work • Creativity and flexibility to thrive under changing priorities and evolving program needs • Strong analytical thinking and problem-solving capabilities • Collaborative mindset with ability to work effectively across diverse teams • Adaptability to work in a fast-paced, innovative environment • Leadership potential to drive independent R+D initiatives • Passion for pushing the boundaries of quantum technology development Join Intel's Quantum Computing Group and be part of a team that's not just researching quantum computing - we're building it. If you're passionate about combining cutting-edge quantum physics with real-world applications and want to work with the resources and expertise of the world's leading semiconductor company, we want to hear from you. Apply today and discover your place in our world-changing work.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:
• Bachelor's degree with 4 years of experience, Master's degree with 3 years of experience, or Ph.D. degree in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies, or Quantum Engineering or related Engineering field
• Must possess 1+ years experience with at least one of the following:
o Electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on-chip/on-package interconnect
o Standard cell design, design automation flow implementation (SKILL, VSR, MSOA or equivalent), and universal process file models and extraction
o Digital design tools and APR based routing design and ability to script and configure APR tools with languages such as TCL
o Designing and taping out designs on a mainstream foundry process PDK including running all industry standard validations such as DRC, ERC, LVS, PEX.
o Implementing PDK collateral and design flows to enable and maintain design environments

Preferred Qualifications:
• 1+ years of experience with:
o Electrical measurement experience with qubit, quantum devices, transistors, or integrated circuits
o Process-Integration experience with qubit or CMOS devices or interconnects
o Experience with dilution refrigerators or other cryogenic systems
o RFIC design or experience with cryogenic control of qubits
o Design of superconducting circuits and superconducting interconnects
o Programming, software, or driver development and scripting for task automation using languages such as Python
o Implementing Machine Learning or AI based digital design routing algorithms
o Working with EDA tool vendors to enable customized design solutions

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, New York, New York, US, Pennsylvania, Allentown, US, Texas, Austin

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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