1,000+ matching jobs for “Design Verification Engineer”How results work Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
+1 location
Pay posted by employer $75,100–$112,700
… of electrical engineering designs through the procurement process Coordination and liaison of electrical design integration and assembly Lead and coordinate integration of hardware in a laboratory environment …
Added Nov 3, 2026
The Role and Impact As a SoC Design Verification Engineer , you will play a critical role in ensuring the functionality and reliability of cutting-edge System-on-Chip …
Added Oct 31, 2026
GHT
GE HealthCare Technologies
Summary The Mechanical Design Engineer is responsible for the design, development, validation, and continuous improvement of mechanical …
Added Oct 27, 2026
The Role and Impact As a CPU Design Verification Engineer , you will play a critical role in ensuring the reliability and functionality of Intel's cutting-edge CPU …
Added Oct 27, 2026
+1 location
… Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff …
Added Oct 27, 2026
In this role, the Electrical Design Engineer will be responsible for the electronic design for high-volume manufacturing, ensuring high quality …
Added Nov 3, 2026
… devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design , KLA's Global Products Group (GPG), which is responsible for creating all of KLA’s metrology and inspection …
Added Oct 15, 2026
NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the …
Added Oct 27, 2026
Pay posted by employer $82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time …
Added Oct 31, 2026
Pay posted by employer $82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time …
Added Oct 31, 2026
Pay posted by employer $145,000–$246,000 per year
… deliver required functionalities Participate in the conception and development of new circuits Define and design composition architecture specifications for new features. Support the creation of schematics and/or RTL …
Added Nov 3, 2026
We are looking for a Formal Verification Engineer within our Hardware team! As a Formal Verification Engineer at NVIDIA, you will verify the design …
Added Oct 27, 2026
3 postings
In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …
Added Oct 5, 2026
2 postings
In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …
Added Oct 5, 2026
+1 location
IC Design Engineer (ICB4) Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions …
Added Oct 21, 2026
… engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build …
Added Oct 27, 2026
In person Full time Regular Pay posted by employer $98,600–$133,400
ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: The Boeing …
Added Oct 12, 2026
Senior Design Engineer Do you enjoy working with complex electro-mechanical systems? Do you have experience defining …
Added Oct 28, 2026
Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …
Added Nov 3, 2026
Pay posted by employer $61,900–$99,000 USD per year
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …
Added Oct 31, 2026
Qualifications · employer excerpt Bachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design. Strong knowledge of one or more of the following areas:IP/subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols.SoC/ASIC design methodology and industry-standard front-end development practices.SoC…
About this opportunity Original employer description
Job Details:
Job Description: Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing technology that reaches people around the globe.
Key Responsibilities
Own DDG internal IP RTL design and development or integrate high-performance and high-bandwidth IP into Client SoC platforms. Define, implement, and deliver new IP features, change requests, and feature enhancements. Drive IP-to-SoC handoff quality, ensuring design completeness, compliance, and readiness for downstream integration. Perform logic and RTL integration into SoC, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral for system and software integration. Develop design solutions and collaborate closely with verification teams to validate functionality, features, and integration readiness. Execute front-end quality checks across RTL static analysis, synthesizability, timing and power convergence, netlist quality, formal equivalence verification, and related design quality milestones. Interpret power specifications and translate power requirements into design considerations, analysis plans, and measurable checks. Support power estimation, analysis, rollup, and convergence. Investigate power issues, identify root causes, and recommend design or flow solutions.
Qualifications: Bachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design. Strong knowledge of one or more of the following areas:IP/subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols. SoC/ASIC design methodology and industry-standard front-end development practices. SoC fabric and interconnect design. RTL design using Verilog and SystemVerilog. Industry front-end and RTL tools, flows, and design methodologies. Experience using AI tools or AI-assisted engineering workflows to improve RTL/Logic development productivity, including design exploration, code generation, review, debug, documentation, and front-end quality checks. Ability to orchestrate efficient development workflows by combining domain expertise, automation, scripting, AI-assisted tools, and structured engineering practices to accelerate delivery while maintaining design quality. Pre-silicon or post-silicon lab debug and power-on experience. Excellent communication, collaboration, problem-solving, and teamwork skills.
Job Type: Experienced Hire
Shift: Shift 1 (Malaysia)
Primary Location: Malaysia, Penang
Additional Locations:
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Full time Regular Silicon Hardware Engineering
