1,000+ matching jobs for “Test Automation Engineer”

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Procter & Gamble

Automation QA Engineer

WARSAW DOWNTOWN OFFICE

We’re looking for a QA Engineer to join our Data & Analytics Platforms RUBIK engineering team. We are searching for self-motivated …

Added Oct 27, 2026

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Rockwell Automation

QA Test Engineer

Mexico City, Mexico +3 locations 2 postings

Full time

As a QA Test Engineer - Manual and Tosca, you will be an important member of Rockwell Automation's Global Quality …

Added Oct 29, 2026

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Nvidia

… through AI, supported by dedicated people and a diverse, collaborative environment. We are seeking a SWQA Test Developer Engineer to join the Mobile QA Group and help deliver high-quality products built on NVIDIA Tegra …

Added Oct 27, 2026

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RTX

Senior Engineer Robotics & Automation

SG-01-SINGAPORE-018 P1 ~ 18 Bedok S Rd ~ 18 BEDOK S RD-018 P1

blends deep automation expertise, strong OT/IT integration capability to realize Collins’ Lights-Out Manufacturing and Factory of …

Added Oct 27, 2026

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Caterpillar

Test and Validation Engineer

Mossville, Illinois

Pay posted by employer$120,994–$146,290 per year

… live. Together, we are building a better world, so we can all enjoy living in it. Caterpillar Inc. seeks Test and Validation Engineer at its facility located at 14009 Old Galena Road, Building L, Chillicothe, IL …

Added Oct 28, 2026

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Abbott Laboratories

Senior Software Test Engineer

Alameda, California, United States

Pay posted by employer$90,000–$180,000

… for diversity, working mothers, female executives, and scientists. THE OPPORTUNITY This Senior Software Test Engineer position works onsite in our Alameda, CA location for Lingo. We are seeking a Software Test …

Added Oct 15, 2026

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Intel

Physical Design Automation Engineer

Bengaluru, Karnataka, India

Full time
Regular

… working on cutting-edge process technologies. We are seeking an experienced Technical Lead - APR Design Automation to develop and optimize RTL-to-GDS (R2G) flows primarily using Cadence Innovus Implementation System, while …

Added Oct 27, 2026

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Jabil

Test Engineer - Liquid Cooling

Florence, Kentucky, United States

Technical Leadership & Engineering Design, develop, and maintain test procedures, test systems, hardware, and software for advanced compute platforms. Lead failure analysis and …

Added Oct 28, 2026

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Dover

Senior Automation Controls Engineer

Milwaukie, Oregon, United States

… in a manner that minimizes the risk of damage to property and injury to the employee and others. The Automation Controls Engineer is an individual contributor responsible for specification, design, qualification, and …

Added Nov 3, 2026

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Abbott Laboratories

Staff SW Test Engineer

Hyderabad, Telangana, India

… reliability and scalability of cloud-native, enterprise-grade platforms. We are seeking a Staff Software Test Engineer to lead verification and validation efforts across our cloud, and mobile platforms within a …

Added Oct 19, 2026

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Kyndryl Holdings

DevOps Engineer - SQL+Automation

Greater Noida, Uttar Pradesh, India

In person

… cloud and mobile applications to seamlessly interact with the mainframe’s core data. Key Responsibilities Automation & Configuration Management Design, develop, and maintain Ansible playbooks, roles, and automation workflows …

Added Oct 27, 2026

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RTX

Automation Engineer - Data Governance

US-NC-REMOTE

… with enterprise data goals. Design, develop, and maintain APIs, API contracts, scripts, and reusable automation components for data governance processes. Automate metadata ingestion, scanning, synchronization, and …

Added Oct 27, 2026

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Analog Devices

Staff ATE Test Engineer

Milpitas, California, United States

Pay posted by employer$130,168–$188,490

… solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, …

Added Nov 3, 2026

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GE Vernova

Lead Test Development Engineer

Stafford, England, United Kingdom

Summary At GE Vernova, we are looking for a Lead Test Development Engineer to join our team in Stafford. You will be the architect behind the test solutions that …

Added Oct 27, 2026

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Leidos Holdings

Automated Test Engineer Expert

Chantilly, Virginia, United States

Pay posted by employer$116,350–$210,325

… level requirements Investigate problems referred by customer support Plan, manage, and track project test efforts Evaluate and develop detailed test plans, procedures, and reports Oversee and perform testing in a …

Added Nov 3, 2026

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Palo Alto Networks

Senior Principal Engineer Test

Office - USA - CA - Headquarters

Test Architecture & Strategy Define and own system-level and platform-level test architecture across multiple …

Added Oct 27, 2026

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Amentum Holdings

Vehicle Battery Test Engineer

Detroit, Michigan, United States

Configuring/Operating/Programming Lynx site automation systems and supplemental site controls and I/O to achieve fully automated testing and 100% error …

Added Nov 3, 2026

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Leidos Holdings

TPS Systems Test Engineer

Washington, District of Columbia, United States

Pay posted by employer$92,300–$166,850

Requirements analysis; software design analysis, specification reviews, user documentation inspection; test planning, test execution (functional, integration, regression and more), test results recording and …

Added Nov 3, 2026

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Nvidia

Senior System Test Engineer

Santa Clara, California, United States

We are looking to hire a System Test Engineer who will work in the test solutions group at NVIDIA developing manufacturing test solutions for …

Added Oct 27, 2026

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RTX

Radio Frequency Test Engineer

Goleta, California, United States

Assist in the development and execution of automated test systems and validation procedures. Troubleshoot and provide accurate rework instructions for the product …

Added Oct 27, 2026

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Intel

Physical Design Automation Engineer

Bengaluru, Karnataka, India

Full time
Regular

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About this opportunity

Original employer description

Job Details:

Job Description:

The Design Technology Platform team at Intel Foundry India is chartered with process technology definition, advanced methodology development, and design prototyping on Intel's latest process nodes. We support Intel's internal and external design customers and offer a unique opportunity to be among the first engineers working on cutting-edge process technologies. We are seeking an experienced Technical Lead - APR Design Automation to develop and optimize RTL-to-GDS (R2G) flows primarily using Cadence Innovus Implementation System, while supporting test chip and foundry IP needs. The ideal candidate will bring deep expertise in Cadence Innovus-based PnR flow development, with working knowledge of Synopsys Fusion Compiler being a strong added advantage. A key aspect of this role will be enabling, deploying, and supporting Cadence Innovus-based APR flows for Intel's internal product design teams as well as external foundry customers who are leveraging Intel's process technology - ensuring robust, scalable, and production-ready flow solutions that meet the design and performance requirements across a diverse customer base. This is an individual contributor (IC) technical leadership role focused on physical design automation tools, flows, and methodologies on leading-edge process nodes. • Lead the development, deployment, and continuous improvement of RTL-to-GDS flows using Cadence Innovus as the primary PnR platform • Define and drive physical design tools, flows, and methodologies including: o Block-level implementation and integration o Floorplanning, placement, CTS, and routing automation o Timing closure methodologies • Develop and maintain Tcl-based scripting and automation to enhance layout productivity within Innovus and related Cadence tools • Evaluate and benchmark Cadence Innovus vs. Synopsys Fusion Compiler flows; provide data-driven recommendations on tool and methodology selection • Enable and support industry-standard static timing analysis (STA) tools for test chips and Foundry IPs (FIPs), and ensure continued support and enhancement • Collaborate with central CAD, design teams, local CAD teams, and EDA vendors (Cadence, Synopsys) to define next-generation PnR methodologies • Work closely with internal and external design customers to understand requirements and deliver robust, scalable automation solutions • Respond to customer/client requests proactively, developing solutions leveraging formal expertise and engineering judgment • Contribute to process node bring-up by validating and refining flows on Intel's latest technology nodes

Qualifications:

Educational Requirements Master's degree in M.Tech or MS in Microelectronics, Electronics Engineering, or an equivalent qualification from a reputed institute, with relevant industry experience in physical design and APR flow development Technical Qualifications Physical Design and APR Expertise Proven hands-on experience in block-level design closure using Cadence Innovus Implementation System as the primary APR tool for end-to-end RTL-to-GDS flows Strong working knowledge of all key physical design stages including Floorplanning covering die size estimation, macro placement and pin assignment, Power Planning covering power grid design, IR drop awareness, ring and stripe strategies, Placement covering timing-driven and congestion-aware placement optimization, Clock Tree Synthesis covering clock tree design, skew and latency optimization, and Routing covering global and detailed routing and DRC-clean routing closure Well-versed with multiple optimization techniques available in Cadence Innovus for achieving design closure, including timing, area, power, and congestion optimizations Ability to guide and mentor the team in resolving complex implementation challenges and providing structured solutions Timing and Constraints Strong understanding of digital timing concepts including setup, hold, clock domain crossing CDC, and multi-mode multi-corner MMMC analysis Ability to analyze and validate design constraints SDC and understand their impact on timing closure Experience with industry-standard STA tools such as Cadence Tempus or equivalent for timing sign-off Layout Closure and Sign-off Demonstrated experience in achieving full layout closure for blocks, ensuring compliance with DRC Design Rule Check, LVS Layout vs. Schematic, Density requirements and Antenna violation fixes Familiarity with physical verification tools and sign-off flows as per process technology specifications Top-Level Integration Good understanding of top-level integration challenges and ability to ensure block-level deliverables meet project-level requirements for both timing and layout closures Experience in managing block-to-top handoffs and resolving integration-level issues effectively Domain Knowledge Strong foundation in VLSI design, digital electronics, and semiconductor device fundamentals Good understanding of digital design timing closure principles and methodologies Knowledge of semiconductor fabrication and process technology will be a distinct added advantage Familiarity with Intel process technology or advanced node design environments is a plus Soft Skills and Behavioral Competencies Strong analytical and problem-solving skills with a structured approach to debugging complex physical design issues Proactive and transparent communication style with the ability to articulate technical challenges and solutions clearly to stakeholders Collaborative mindset with demonstrated ability to work effectively in a diverse, cross-functional, and geographically distributed team environment Ability to work across multiple domains including design, CAD, and EDA vendor teams Leadership and Experience Leadership experience in driving block-level closure and physical design sign-off for tape-out is strongly preferred Demonstrated track record of silicon success having contributed to or led designs that have been successfully taped out and validated in silicon is highly desirable

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Keywords also found in description

Full time
Regular
Silicon Hardware Engineering

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