272 matching jobs for “SoC Design Verification Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Nvidia

DFT Engineer

China, Shanghai

NVIDIA is seeking a highly motivated DFT Engineer to join our silicon engineering team. In this role, you will work closely with Design, Test, CAD, and …

Added Oct 27, 2026

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Intel

Emulation Engineer

Virtual India

The Role and Impact As an Emulation Engineer, you will play a critical role in advancing pre-silicon verification processes by developing and enhancing …

Added Oct 27, 2026

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Broadcom

Senior DFT engineer

Singapore-Yishun 6 postings

Full time
Regular

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be …

Added Nov 3, 2026

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Marvell Technology

… fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from …

Added Nov 3, 2026

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Intel

FPGA Prototyping Engineer

Malaysia, Penang

The Role and Impact As an Emulation Engineer, you will play a critical role in advancing Intel's silicon development by building and optimizing …

Added Oct 29, 2026

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Intel

FPGA Prototyping Engineer

Malaysia, Penang

The Role and Impact Join Intel as an Emulation Engineer and play a key role in developing and optimizing emulation and FPGA models that accelerate RTL development …

Added Oct 29, 2026

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Broadcom

Staff Engineer

Bengaluru, Karnataka, India

Full time
Regular

Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, …

Added Oct 5, 2026

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Broadcom

Senior Engineer

Bengaluru, Karnataka, India 2 postings

Full time
Regular

Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, …

Added Oct 5, 2026

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Broadcom

DFT Lead Engineer

San Jose, California, United States 2 postings

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, …

Added Nov 4, 2026

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Intel

Pre-Si Validation Engineer

Toronto, Ontario, Canada

Pay posted by employer$153,910–$217,280 CAD per year

The Role and Impact Join Intel's cutting-edge team as a Formal Verification Engineer, where you will play a pivotal role in ensuring the quality and reliability of our next-generation …

Added Oct 28, 2026

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Nvidia

Senior JTAG Methodology Engineer

Santa Clara, California, United States

We are now looking for a Senior JTAG Methodology Engineer! As a Senior JTAG Methodology Engineer, you will architect and develop the test methodologies that make our …

Added Oct 27, 2026

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Analog Devices

Staff DFT Engineer

Bengaluru, Karnataka, India

… LBIST, MBIST, boundary scan, and test access strategies Drive testability requirements early in the RTL design phase Balance coverage, test time, power, area, and schedule tradeoffs DFT Implementation (End-to-End …

Added Nov 3, 2026

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RTX

Senior Electronics Engineer

Harlow, England, United Kingdom

… United Kingdom

 Location: Harlow, Essex

 Position Role Type: Onsite Senior Electronics Engineer Harlow | Hybrid Working (Minimum 3 Days On Site) Design cutting-edge defence technology that protects …

Added Oct 27, 2026

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Nvidia

DFT Engineer (RDSS Intern) - 2027

Taiwan, Taipei +1 location

. NVIDIA is seeking phenomenal engineers to improve our verification methodology, so we can validate the world’s largest design efficiently. This position offers the …

Added Oct 27, 2026

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Booz Allen Hamilton

FPGA Engineer

Annapolis Junction, MD

Pay posted by employer$77,600–$176,000

FPGA Engineer The Opportunity: We need you, an electrical engineer, with an understanding of embedded system design, FPGA …

Added Oct 27, 2026

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Nvidia

Senior Full-Chip RTL Integration Engineer

Santa Clara, California, United States +1 location

… adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for …

Added Oct 27, 2026

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Thermo Fisher Scientific

Sr. Electronics Engineer - FPGA

Guangdong, China

… Patheon and PPD. For more information, please visit www.thermofisher.com . Job Title: Senior Electronics Engineer - FPGA Location: Guangzhou Reports to: Senior Manager, Manufacturing Engineering Group/Division Summary: …

Added Oct 16, 2026

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Intel

GPU Validation Engineer

Toronto, Ontario, Canada

Pay posted by employer$153,910–$217,280 CAD per year

… about technology and dedicated to excellence. We are seeking a skilled and experienced GPU Validation Engineer to join our dynamic team. This role requires regular onsite presence to effectively collaborate with …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

Santa Clara, California, United States

… join a world-class team and make a significant impact in the semiconductor industry! What You'll Be Doing: Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms. Own and work with …

Added Oct 27, 2026

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Nvidia

Board Product Development Engineer

Santa Clara, California, United States

Join NVIDIA as a Product Development Engineer, where you’ll be at the forefront of innovation! This is an outstanding opportunity to work on new product …

Added Oct 27, 2026

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Marvell Technology

Principal Engineer, DFT

Bengaluru, Karnataka, India

Regular

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What We're Looking For · employer excerpt

We are seeking a highly motivated and experienced Principal Engineer – Design for Test (DFT) to lead DFT architecture, implementation, and signoff activities for complex SoC and ASIC designs. The ideal candidate will have deep expertise…

About this opportunity

Original employer description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from Marvell help customers address the growing demands of AI, cloud computing, edge computing, 5G networks, and next-generation data centers. Engineers within the Connectivity Business Unit work on cutting-edge silicon design, firmware, software, system validation, and platform development, collaborating across global teams to deliver products that connect billions of devices and accelerate digital transformation.

Joining the Connectivity Business Unit offers the opportunity to work on complex technical challenges, influence next-generation connectivity technologies, and contribute to products deployed at global scale.

What You Can Expect

Define and drive DFT architecture and implementation strategies for complex SoC/ASIC designs.
Develop and implement scan, compression, MBIST, and other DFT features to achieve test coverage and manufacturing quality goals.
Execute and support scan insertion, DFT verification, and ATPG flows.
Collaborate closely with RTL, verification, physical design, timing, and product engineering teams throughout the design lifecycle.
Create and maintain DFT-related timing constraints and signoff requirements.
Perform DFT timing analysis and debug timing-related issues.
Drive DFT methodology improvements and contribute to flow automation.
Provide technical leadership and mentorship to junior engineers.

What We're Looking For

We are seeking a highly motivated and experienced Principal Engineer – Design for Test (DFT) to lead DFT architecture, implementation, and signoff activities for complex SoC and ASIC designs. The ideal candidate will have deep expertise in DFT methodologies, scan insertion, ATPG, timing constraints, and test architecture development, with a proven track record of delivering high-quality silicon products.

Required Qualifications

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in Design for Test (DFT) for ASIC/SoC development.
Strong expertise in DFT methodologies, including scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan and testability concepts.
Hands-on experience with Siemens EDA Tessent tools.
Strong experience with synthesis and scan insertion tools.
Solid understanding and hands on experience of Static Timing Analysis (STA) and timing closure concepts.
Experience creating and managing SDC (Synopsys Design Constraints) files for DFT implementation and timing signoff.
Strong debugging, problem-solving, and analytical skills.
Excellent communication and collaboration skills.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Keywords also found in description

Design Engineering
Regular

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.