648 matching jobs for “ASIC Design Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Nvidia

Verification Engineer - PCIE

Bengaluru, Karnataka, India

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s …

Added Oct 27, 2026

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Nvidia

… excellent judgment matters as much as technical depth! We are the Silicon Power Team within the Silicon Co-Design Group. We architect and deliver groundbreaking solutions for productizing NVIDIA's chips across consumer, …

Added Oct 27, 2026

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Nvidia

Verification Engineer, PCIE

Bengaluru, Karnataka, India

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s …

Added Oct 27, 2026

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Marvell Technology

Hardware Applications Engineer

Santa Clara, California, United States

Regular

… application engineering position focuses on resolving customer issues on their HW/platform, customer design enablement, bring-up, and manufacture production. The candidate should have strong working knowledge of the …

Added Nov 3, 2026

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Cisco Systems

Silicon Validation Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 30, 2026

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Analog Devices

Staff DFT Engineer

Bengaluru, Karnataka, India

… LBIST, MBIST, boundary scan, and test access strategies Drive testability requirements early in the RTL design phase Balance coverage, test time, power, area, and schedule tradeoffs DFT Implementation (End-to-End …

Added Nov 3, 2026

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Cisco Systems

DevOps Infrastructure Engineer

Caesarea, Israel

DevOps Infrastructure Engineer Cisco Silicon One is seeking a highly motivated and experienced DevOps Infrastructure Engineer to join our …

Added Oct 27, 2026

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Marvell Technology

Senior Staff Hardware Engineer

Taipei

Full time
Regular

… beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Hardware Design Senior Staff Engineer will serve as a key member of the Hardware Design team within the Operations PE/TE …

Added Nov 3, 2026

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Nvidia

Senior Formal Verification Engineer - LPU

Canada, Remote

… work. Join us and discover how you can build a lasting impact on the world! As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will …

Added Oct 31, 2026

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Marvell Technology

Principal Engineer, ATE Test Development Engineer

Santa Clara, California, United States

Full time
Regular

… Issues, Driving Cutting‑Edge Test Capability and ensuring Products meet the Highest Quality Standards Design and Develop High‑Speed ATE Hardware Supporting Data Rates above 112 Gbps, Advancing Next‑Generation Test …

Added Nov 3, 2026

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Cisco Systems

Senior Hardware Engineer (Datacenter Switch)

Hsinchu, Taiwan, Taiwan +1 location

Added Oct 29, 2026

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Nvidia

Senior DFT Engineer

Santa Clara, California, United States

… This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions …

Added Oct 27, 2026

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Nvidia

Senior STA Signoff Methodology Engineer

Santa Clara, California, United States +1 location

… how you can make a lasting impact on the world. We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a …

Added Oct 27, 2026

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Marvell Technology

Principal Hardware Engineer - 3rd Party IP Engineer

Morrisville, North Carolina, United States +5 locations

Full time
Regular

… in this position, you will engage all parts of Marvell. Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of …

Added Nov 3, 2026

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Nvidia

Senior Formal Verification Engineer - LPU

US, CA, Remote +4 locations

Added Oct 31, 2026

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Broadcom

R&D Engineer Mechanical

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

As a Principal Hardware Engineer, you will design, develop, and deliver Mechanical assemblies, including full chassis design for Ultra …

Added Oct 5, 2026

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Broadcom

R&D Hardware Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$101,000–$162,000 USD per year

As a Hardware Engineer, you will design, develop, and deliver Ultra High-performance electronic products. In addition, you may …

Added Oct 9, 2026

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Nvidia

Senior Physical Verification Engineer

Israel, Tel Aviv +1 location

… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …

Added Oct 27, 2026

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Nvidia

Senior QA Software Engineer, Networking

Warsaw, Mazovia, Poland +1 location

What if your Python automation caught a critical ASIC bug before the physical silicon was even manufactured? At NVIDIA, our simulation platforms make that happen …

Added Oct 27, 2026

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Nvidia

Senior Package Layout Engineer - Hardware

Bengaluru, Karnataka, India

… in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will …

Added Oct 27, 2026

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Marvell Technology

Principal Engineer, ATE Test Development Engineer

Santa Clara, California, United States

Full time
Regular

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What We're Looking For · employer excerpt

Bachelor’s degree in Electrical Engineering, Computer Engineering, or any related discipline
5 to 10 years of experience in Semiconductor Test Engineering, with Demonstrated Technical Leadership on Complex SoC/ASIC/analog Test Programs
Strong Hands-on Experience with Advantest 93000 ATE Platforms and SmarTest-8 Test Program Development
Deep understanding of DFT techniques: scan, BIST, boundary scan/JTAG, ATPG, SSN, and Test Coverage Analysis
Experience with Spanning New Product Introduction (NPI), Silicon Bring-up, Characterization, Correlation, and High‑Volume Manufacturing proven Technical Leadership in High‑Speed and High‑Power Semiconductor Test Development for AI,…

7 more in the full description below.

About this opportunity

Original employer description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Principal Test Engineer role offers Technical Leadership in Architecture and Scalability of Automated Test Equipment (ATE) test solutions for Hyperscale devices.

This position outlines the Hyperscale Test Strategy, facilitates Cross-Functional Alignment, and oversees the development of ATE Test Programs that ensure robust Qualification, Comprehensive Test Coverage, and efficient High-Volume
Manufacturing.

As the primary Technical Authority, the role guarantees that Test Methodologies, Infrastructure, and execution adhere to the Performance, Quality, and Scalability Requirements outlined in the Product Roadmap.

What You Can Expect

Define and own the End-to-End Test Strategy across Wafer Sort, Final Test, Production, and Wafer Sort on the Advantest 93K platform and System-Level Test (SLT) for new Silicon Test Programs
Lead the Development of ATE Test Solutions, Silicon Bring-up and Characterization on new Tape-Outs, including Bench Validation, Correlation to simulation, Debug of First-Silicon Issues, Driving Cutting‑Edge Test Capability and ensuring Products meet the Highest Quality Standards
Design and Develop High‑Speed ATE Hardware Supporting Data Rates above 112 Gbps, Advancing Next‑Generation Test Methodologies and enabling Future‑Ready Semiconductor Products
Create Comprehensive Test Plans and Methodologies aligned with Stringent Product Specifications, ensuring Robust Validation and Consistent Product Performance
Collaborate closely with DFT, DFM and Design teams to Review Testability and Test Strategies, Contributing to Improved Yield, Optimized Test Methodologies, and Cross‑Functional Innovation
Convert Design‑level Test Content into ATE‑Ready Test Patterns, ensuring Seamless Transition from Simulation to Production Environments
Drive Test Flow Optimization, Reducing Test Time, Eliminating Redundant Steps, Improving Yields, and Releasing
High‑Quality Production Test Programs in Partnership with Cross‑Functional Engineering Teams
Manage Cost-of-Test Initiatives across the Product Lifecycle
Partner with Product Engineering, OSAT/foundry Test Floors on Test Program Transfer, Correlation, and Production Ramp Support
Represent Test Engineering in Design Reviews, Providing Testability, Test Coverage, and Cost-of-Test input early in the Design Cycle
Support Customer-Returns Technical Engagements (RMA), including Debug of Customer-Reported Silicon Issues and Test Escape Investigations

What We're Looking For

Bachelor’s degree in Electrical Engineering, Computer Engineering, or any related discipline
5 to 10 years of experience in Semiconductor Test Engineering, with Demonstrated Technical Leadership on Complex SoC/ASIC/analog Test Programs
Strong Hands-on Experience with Advantest 93000 ATE Platforms and SmarTest-8 Test Program Development
Deep understanding of DFT techniques: scan, BIST, boundary scan/JTAG, ATPG, SSN, and Test Coverage Analysis
Experience with Spanning New Product Introduction (NPI), Silicon Bring-up, Characterization, Correlation, and High‑Volume Manufacturing proven Technical Leadership in High‑Speed and High‑Power Semiconductor Test Development for AI, Networking, and Advanced Hyperscale Products
Deep expertise in ATE Test Methodologies, Silicon Process Fundamentals, DFT (Design-for-Test), DFM (Design-for- Manufacturing), High‑Speed SerDes, and High‑Power ATE testing.
Track record of Building Scalable and Reusable ATE Test Libraries and Test Methods for MCM, CPC, and CPO Product Lines
Proficiency in Scripting Test Automation, Data Analysis, and Computer Languages like Java, C/C++, Perl, and Python
Excellent Cross-Functional Communication Skills, with experience Presenting Yield/Quality Data to Senior Leadership and Customers
Demonstrates Strong Cross-Functional Communication Skills, with experience in Presenting Yield and Quality Data to Senior Leadership and Customers
Possesses effective Communication Abilities, Strong teamwork, and Problem Solving Skills
Self-motivated, Adaptable, and Capable of Thriving in Fast-Paced, Dynamic Engineering Environments

Expected Base Pay Range (USD)

136,880 - 205,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Keywords also found in description

Full time
Regular
Test & Product Engineering

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