1,000+ matching jobs for “Design Verification Engineer”How results work Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
The Senior Design Mechanical Engineer is responsible for supporting the design, development, validation, and release of …
Added Oct 28, 2026
… that align product capabilities to the needs of our customer. We will empower our people to leverage design commonality and innovation, balancing risk and rigor, to achieve predictable and affordable solutions. We …
Added Oct 27, 2026
Pay posted by employer $141,300–$207,233 per year
… high-impact work across your area of expertise. KLA is seeking an experienced and motivated Sr. FPGA Engineer to join our electrical engineering team! Our designs employ innovative combination of low noise analog to …
Added Oct 15, 2026
+1 location
Pay posted by employer $121,900–$195,000 USD per year
… SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design , PPA optimization, clock domain crossing (CDC) analysis and Reset Domain crossing (RDC). Beyond technical …
Added Oct 5, 2026
… on manufacturing and field failures and implement corrective and preventive actions. Collaborate with design , manufacturing, quality, supply chain, and test engineering teams to resolve product and process issues. …
Added Oct 15, 2026
Pay posted by employer $198,000–$336,000 per year
Design , implement, and debug complex RTL logic and integrate IP into larger subsystems Support front-end design …
Added Nov 3, 2026
… that align product capabilities to the needs of our customer. We will empower our people to leverage design commonality and innovation, balancing risk and rigor, to achieve predictable and affordable solutions. We …
Added Oct 27, 2026
Pay posted by employer $141,300–$240,200 per year
… by delivering high-impact work across your area of expertise. We are seeking a skilled Mechanical Design Engineer to lead the design and development of precision mechanical systems for advanced semiconductor …
Added Oct 15, 2026
An opportunity exists for a Senior MMIC Design Engineer to join the Microelectronics Department at Raytheon. Our team designs custom integrated circuits …
Added Oct 27, 2026
Pay posted by employer $106,700–$156,500 per year
… priorities by delivering high-impact work across your area of expertise. KLA is seeking a Manufacturing Design Engineer (MDE) to join the BBP Final Integration Systems team. In this role, you will support the …
Added Oct 15, 2026
+1 location
Pay posted by employer $141,910–$200,340 USD per year
As a GPU Logic Design Engineer at Intel, you will play a critical role in shaping the future of graphics and compute …
Added Oct 30, 2026
… with a bright future. This is an excellent opportunity to join a high performing team, working on the design of the next generation of automotive BMS chips. The designs include industry-leading low power radio …
Added Nov 3, 2026
will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines. …
Added Nov 3, 2026
… Make the choice to join us today. The GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking. The team collaborates with the …
Added Oct 27, 2026
HPE
Hewlett Packard Enterprise
Pay posted by employer $158,500–$321,000 USD per year
… detailed micro-architecture specification that meets the power/area requirements . You will i mplement the design using Verilog or System Verilog W rite functional coverage/SVA to help verification catch corner case bugs. …
Added Nov 9, 2026
Pay posted by employer $186,200–$273,067 per year
… work across your area of expertise. We are seeking an experienced and highly influential Staff System Design Engineer to lead the architecture, development, and performance delivery of next-generation Xray - based …
Added Oct 15, 2026
Design , analyze (including thermal considerations), simulate, and test power conversion circuitry potentially …
Added Oct 27, 2026
Pay posted by employer $61,300–$122,700
Job Title Software Design Quality Engineer Working at Abbott At Abbott, you can do work that matters, grow, and learn, care for …
Added Oct 15, 2026
The Design Technology Platform team at Intel Foundry India is chartered with process technology definition, advanced …
Added Oct 27, 2026
+1 location
Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire …
Added Oct 27, 2026
Minimum Qualifications · employer excerpt BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies. Experience with TSV(Through-Silicon Via) interface circuit design or high-speed memory interface design(NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity. Advanced knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB(Energy per Bit) optimization in the context of… Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design… Applying AI to daily work and design work flow to improve quality and efficiency.
About this opportunity Original employer description Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Position Overview
The Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines.
Responsibilities
Design and optimize TSV(Through-Silicon Via) interface circuits connecting memory die to logic die including Rx/Tx circuit for internal TSV channels, impedance matching and timing margin analysis. Develop and characterize TSV electrical models and define circuit design constraints for datapath interface. Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis Define and implement power integrity requirements using TSV for highly parallel IO and array operations Design and verify TSV-specific DFT (Design for Testability) circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic Interface with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks. Develop clocking and synchronization strategies for the highly parallel internal bus including wave pipeline design, clock distribution, and skew management Implement and optimize column redundancy and lane repair schemes compatible with HBM like highly parallel bus architecture Define timing budgets and perform timing analysis across the full internal datapath under PVT variations Support post-silicon validation, debug and correlation activities; identify schematic edits and drive necessary tape-out revisions. Collaborate with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan Communicate with project integration and other functional teams in design on specifications of major block interfaces Communicate with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging. Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations. Document and review final results with experts and stakeholders
Minimum Qualifications
BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies. Experience with TSV(Through-Silicon Via) interface circuit design or high-speed memory interface design(NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity. Advanced knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB(Energy per Bit) optimization in the context of 3D-stacked memory architectures. Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design and non-design stakeholders Applying AI to daily work and design work flow to improve quality and efficiency.
Preferred Qualifications
Hands on experience in utilizing AI to improve quality of design and efficiency Experience on chip level PDN optimization Comprehensive understanding on CMOS device and device reliability Comprehensive understanding on CMOS BSIM model and CMOS target for high speed IO operation Experience with signal/power integrity, power delivery network design, physical design
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.[email protected]
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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