373 matching jobs for “ASIC Verification Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own …

Added Oct 27, 2026

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Cisco Systems

ASIC Physical Design Engineer

Caesarea, Israel

Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You …

Added Oct 28, 2026

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Nvidia

Senior ASIC Power Engineer

Santa Clara, California, United States +3 locations

We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and …

Added Oct 31, 2026

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Cisco Systems

… and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure …

Added Oct 27, 2026

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Micron Technology

STAFF ASIC Design Engineer

Hsinchu - Chang Yih, Taiwan

… design automation using Python or other programming languages. Collaborate with SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams. Work closely with software and systems teams to ensure …

Added Nov 3, 2026

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Micron Technology

Principal Engineer, ASIC Design

San Jose, California, United States

Pay posted by employer$198,000–$336,000 per year

… front-end design flow including lint, CDC, synthesis, and ECO activities Collaborate with SOC design, verification, STA, and physical design teams to deliver high-quality silicon Develop automation scripts to improve …

Added Nov 3, 2026

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Broadcom

Principal Physical Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …

Added Oct 25, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: …

Added Oct 12, 2026

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Cisco Systems

ASIC DFT Engineer

Austin, Texas, United States +1 location

Pay posted by employer$139,300–$203,600

… Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development - Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post …

Added Oct 29, 2026

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Nvidia

ASIC Design Engineer - Hardware

Austin, Texas, United States

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering …

Added Oct 27, 2026

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Broadcom

ASIC Design - Floorplan Engineer

Fort Collins, Colorado, United States

Full time
Regular

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing …

Added Oct 31, 2026

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Hewlett Packard Enterprise

Principal ASIC Design Engineer

Sunnyvale, California, United States

Pay posted by employer$181,000–$367,000 USD per year

… and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through …

Added Nov 3, 2026

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Nvidia

Senior Physical Verification Engineer

Israel, Tel Aviv +1 location

… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …

Added Oct 27, 2026

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Marvell Technology

Architecture ASIC Engineer

Córdoba, Cordoba, Argentina

Full time
Regular

… systems at different levels of detail in Matlab, C++, and Python Define, implement and execute functional verification and validation of the design Write thorough documentation Present and defend your decisions and results to …

Added Nov 3, 2026

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Cisco Systems

Senior Design Verification Engineer

Belgrade, Central Serbia, Serbia

Meet the Team Join our SiliconOne team in Serbia, specializing in ASIC functional verification for Cisco Silicon One chips—high-performance networking chips utilized by major …

Added Oct 27, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be …

Added Oct 5, 2026

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Hewlett Packard Enterprise

ASIC Principal Design Engineer

Bengaluru, Karnataka, India

Added Nov 3, 2026

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Nvidia

Senior System Verification Engineer

Austin, Texas, United States +1 location

… as well as its largest total available market opportunity. We are now looking for a highly motivated engineer to join this dynamic and innovative platform verification team. In this role, you will apply your RTL …

Added Oct 27, 2026

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Nvidia

Verification Engineer - GPU Fullchip

Bengaluru, Karnataka, India

… NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. …

Added Oct 27, 2026

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Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

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Required Qualifications · employer excerpt

BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
Expert SystemVerilog RTL skills.
Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
Scripting proficiency (Python, C/C++, Perl, bash or tcsh).

3 more in the full description below.

About this opportunity

Original employer description

Our Mission

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.

Who We Are

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us!

We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes.

Job Summary

About the Role

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals.

What You’ll Do

Write clear design and micro-architecture specifications.
Design SystemVerilog RTL that meets area, performance, and power targets.
Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
Innovate: pilot AI-driven design or verification flows that cut schedule risk.

Qualifications

Required Qualifications

BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
Expert SystemVerilog RTL skills.
Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
Demonstrated strength in:
- Defining micro-architecture from high-level requirements.
- Datapath design expertise for intricate synch/asynch digital logic.
- Debugging across simulation, emulation, and silicon.
- Analyzing timing, power, and area reports and driving fixes.
Demonstrated proficiency or active experience integrating modern AI tools (e.g., LLM coding assistants, automated test generators, or ML-enhanced EDA features) into hardware design, scripting, or verification workflows.
Excellent leadership, collaboration, and written/verbal communication.

Preferred / Nice-to-Have

Networking or cybersecurity domain knowledge.
Experience with search-algorithm accelerators.
Formal-verification ownership.
Hands-on silicon validation and lab bring-up.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/com-missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

$156,400.00 - $253,000.00/yr

Our Commitment

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected].

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.

Is role eligible for Immigration Sponsorship?: Yes

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Keywords also found in description

Engineering Function

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