783 matching jobs for “Full-stack Engineer 4”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

Senior Technical Marketing Engineering Leader

Milpitas, California, United States

Pay posted by employer$194,600–$285,700

… realities that empower our customers to lead in the AI era. Your Impact As a Senior Technical Marketing Engineer and Technical Leader, you will serve as the primary technical authority for our AI infrastructure platform, …

Added Oct 27, 2026

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Capital One Financial

Manager, Data Science - Model Risk Office

McLean, Virginia, United States

… Computer Science, or a related quantitative field) or an MBA with a quantitative concentration plus 4 years of experience performing data analytics A PhD in a quantitative field (Statistics, Economics, …

Added Oct 31, 2026

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Capital One Financial

Manager, Data Scientist -Financial Services- Pricing

Plano, Texas, United States +1 location

Added Oct 29, 2026

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Capital One Financial

Manager, Data Scientist - Card Mainstreet

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Director, Data Scientist

McLean, Virginia, United States +1 location

… Operations Research, Analytics, Mathematics, Computer Science, or a related quantitative field) plus 4 years of experience performing data analytics At least 4 years of experience leveraging open source …

Added Oct 27, 2026

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Capital One Financial

Manager, Data Scientist - Credit Review

McLean, Virginia, United States +5 locations

Added Oct 27, 2026

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Capital One Financial

Manager, Data Scientist - Model Risk Office

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Director, Data Scientist - US Card

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Senior Manager, Data Scientist - Card Fraud Prevention

McLean, Virginia, United States +1 location

… Preferred Qualifications: PhD in “STEM” field (Science, Technology, Engineering, or Mathematics) plus 4 years of experience in data analytics At least 1 year of experience working with AWS At least 1 year of …

Added Oct 27, 2026

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Nvidia

Power Integrity Architect

Santa Clara, California, United States

… growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you! #LI-Hybrid Your base salary will be …

Added Oct 27, 2026

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Cisco Systems

Account Executive - Splunk (Mid-Atlantic Region)

McLean, Virginia, United States +13 locations

Pay posted by employer$269,300–$360,800

… for non-exempt employees 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid …

Added Oct 31, 2026

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Distinguished Technologist - Enterprise Integration and Platform Native AI

Spring, Texas, United States +1 location

Full time
Reg Employee

Pay posted by employer$182,750–$292,400 USD per year

… Employee assistance program Flexible spending account Life insurance Generous time off policies, including; 4-12 weeks fully paid parental leave based on tenure 11 paid holidays Additional flexible paid vacation and …

Added Oct 12, 2026

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Booz Allen Hamilton

Observability Platform Architect

McLean, Virginia, United States

Pay posted by employer$86,800–$198,000

… or security boundary, and managing the drift and duplication that creates ITIL 5 Foundation or ITIL 4 Practitioner: Monitoring and Event Management Certification Compensation At Booz Allen, we celebrate your …

Added Oct 27, 2026

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Stanley Black & Decker

Senior CAD Designer

Towson, Maryland, United States

Full time
Regular

Pay posted by employer$63,700–$102,600

… & metal stamping preferred Good organization and communication skills. Ability to work with more than one engineer and handle multiple assignments concurrently. The Job As a Senior CAD Designer, you’ll be part of our …

Added Oct 27, 2026

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Capital One Financial

Manager, Data Science - US Card - Marketing

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Director, Data Science

Toronto, Ontario, Canada

Added Oct 27, 2026

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Capital One Financial

Manager, Data Science

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Manager, Data Scientist - Recommendation & Personalization Systems

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Director, Data Science

McLean, Virginia, United States +4 locations

Added Oct 27, 2026

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Capital One Financial

Director, Data Science

McLean, Virginia, United States +4 locations

Added Oct 27, 2026

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Nvidia

Power Integrity Architect

Santa Clara, California, United States

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About this opportunity

Original employer description

The Silicon Co-Design Group is hiring a Voltage Noise Co-Design Lead to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, platform, and software— translating product noise targets into shipped specifications and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment.

What you'll be doing:

Architect voltage-noise mitigation across the full stack — silicon, package, board, platform, software — and own the co-design trade-offs between them.
Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Architecture, ASIC, and platform teams. You're the connective tissue across the codesign web.
Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is.
Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them.
Lead show-stopper noise bugs during bringup. The critical issues stop with you.
Drive architecture-level codesign tradeoffs across V/F <-> Power <-> Noise <-> Reliability <-> Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives.

What we need to see:

BS / MS / PhD in EE, CE, or related (or equivalent experience).
5+ years in silicon power integrity, voltage noise, or PDN.
Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
Hands-on silicon experience: bringup, characterization, correlation. You're comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
Strong Sim-to-Si correlation instincts — the field of figuring out which side of the equals sign is wrong.
System-level objectivity. You're willing to make the call that's right for the product even when no single component team agrees with you.
Multi-functional collaboration in a matrixed environment. You can drive a decision through five collaborators without burning bridges, and you write it down when you're done.
Spec rigor. We live in spec lock, sign-off, and OPP closure — the work isn't done until it's documented and shipped.

Ways to stand out from the crowd:

Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation.
Hands-on with groundbreaking GPU, CPU, or AI accelerator silicon — Hopper / Blackwell / Rubin-class or hyperscaler equivalents.
ML/AI applied to noise modeling, transient prediction, droop response, or feature optimization. We're rebuilding our toolchain around AI, and noise is squarely in scope.
Multi-rail, multi-domain PDN ownership at SoC level — die + package + board co-optimization in production.
Track record of codifying methodology into reusable workflows or tooling.

Our team is at the forefront of silicon innovation, advancing groundbreaking technologies. We offer a dynamic work environment where your contributions will directly impact the company's success. Join us to advance your career in a role where you can truly make a difference. With competitive salaries and a generous benefits package, we are widely considered one of the technology industry’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us, and due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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