272 matching jobs for “SoC Design Verification Engineer”

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

The Role and Impact: As a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly …

Added Oct 27, 2026

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Nvidia

Senior Verification Engineer – High Speed Coherent Interconnect Hub

Santa Clara, California, United States

NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …

Added Oct 27, 2026

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Nvidia

ASIC Verification Engineer - New College Grad 2027

Santa Clara, California, United States

… Come join the team and see how we can make a lasting impact on the world. We are seeking to hire a ASIC Verification Engineer - New College Grad 2027 to contribute to the design verification activities that support the …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

Santa Clara, California, United States +1 location

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity …

Added Oct 27, 2026

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Intel

Physical Design Clocking Engineer

Santa Clara, California, United States

Pay posted by employer$105,650–$149,150 USD per year

As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming …

Added Nov 4, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you …

Added Oct 5, 2026

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Nvidia

ASIC Design Engineer - Performance Monitoring

Bengaluru, Karnataka, India

NVIDIA System-On-Chip (SOC) group is hiring for an ASIC Design Engineer! The complexity of the chips we build has increased manifold …

Added Oct 27, 2026

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Micron Technology

STAFF ASIC Design Engineer

Hsinchu - Chang Yih, Taiwan

Design, implement, and debug complex logic designs. Integrate your IP into larger and more complex IPs. Support …

Added Nov 3, 2026

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Cisco Systems

ASIC Physical Design Engineer

Armenia

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer - DFT

Santa Clara, California, United States

We are now looking for a Senior ASIC Design Engineer to join our DFT team! NVIDIA has continuously reinvented itself over two decades. Our invention of …

Added Oct 27, 2026

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Analog Devices

Staff Engineer, Digital Design Engineering

China, Beijing, Haidian, Xixiaokou

… RTL development, synthesis, timing closure, DFT collaboration, and close partnership with physical design teams to deliver robust, production‑ready designs. Key Responsibilities: Define and develop system-level …

Added Nov 3, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

The Role and Impact : As a GPU Logic Design Engineer, you will play a pivotal role in developing and optimizing the RTL design for cutting-edge …

Added Oct 27, 2026

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Nvidia

Senior Physical Design Engineer

Westford, Massachusetts, United States

… and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high …

Added Oct 27, 2026

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Broadcom

Digital Design RTL Engineer

Fort Collins, Colorado, United States +1 location

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

… SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization, clock domain crossing (CDC) analysis and Reset Domain crossing (RDC). Beyond technical …

Added Oct 5, 2026

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Nvidia

ASIC Clocks Verification Engineer - New College Grad 2026

Santa Clara, California, United States

… Make the choice to join us today. The GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking. The team collaborates with the …

Added Oct 27, 2026

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Micron Technology

Principal Engineer, ASIC Design

San Jose, California, United States

Pay posted by employer$198,000–$336,000 per year

Design, implement, and debug complex RTL logic and integrate IP into larger subsystems Support front-end design …

Added Nov 3, 2026

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Intel

GPU Logic Design Engineer

Folsom, California, United States +1 location

Pay posted by employer$141,910–$200,340 USD per year

As a GPU Logic Design Engineer at Intel, you will play a critical role in shaping the future of graphics and compute …

Added Oct 30, 2026

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Nvidia

Senior Mixed-Signal Design Engineer

Santa Clara, California, United States

We are looking for an Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the …

Added Oct 31, 2026

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Intel

IP RTL Senior Design Engineer

Bengaluru, Karnataka, India

The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified …

Added Oct 27, 2026

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Intel

GPU Senior Logic Design Engineer

Bengaluru, Karnataka, India

GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer - DFT

Santa Clara, California, United States

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About this opportunity

Original employer description

We are now looking for a Senior ASIC Design Engineer to join our DFT team!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.

Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs
Develop, deploy, and enhance DFT methodologies for scalability and future product needs
Define and align feature sets by working closely with architects, platform, and software teams
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration
Create and execute test plans to support both functional and DFT full-chip verification
Support post-silicon bring-up and validation efforts including debug and issue resolution
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance

What we need to see:

BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience
8+ years of hands-on experience in SoC architecture, RTL design, and verification
Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus)
Experience in DFT design, methodology, and implementation
Familiarity with related domains such as clocking, STA, place & route, and power optimization
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis
Proficiency in scripting languages such as Python, Perl, or Tcl
Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges

Ways to Stand out from the Crowd:

Experience with UVM-based verification environments
Experience designing fuse, eFuse, or on-chip security blocks
Proven track record of successfully architecting DFT IPs across multiple product generations

Why Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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