116 matching jobs for “Senior DFT Engineer”

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Broadcom

Senior DFT engineer

Yishun New Town, Singapore

Full time
Regular

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for …

Added Oct 9, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality …

Added Oct 27, 2026

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Nvidia

… and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

… Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

Added Oct 27, 2026

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Intel

Senior ASIC DFT Engineer

Israel, Haifa

… rigorous thinking, and want real scope and short feedback loops, you'll feel right at home here. This is a senior, hands-on role with broad technical influence. You will own central DFT aspects in our new family of chips …

Added Oct 27, 2026

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Nvidia

Senior DFT Verification Engineer

Israel, Yokneam +1 location

NVIDIA is looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies. As a design …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer - DFT

US, CA, Santa Clara

We are now looking for a Senior ASIC Design Engineer to join our DFT team! NVIDIA has continuously reinvented itself over two decades. Our …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer - Post Silicon

US, CA, Santa Clara +1 location

As a Senior DFT Engineer - Post-Silicon , you will take pioneering DFT capabilities beyond implementation—connecting silicon …

Added Oct 27, 2026

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Nvidia

Senior DFT Power Methodology Engineer

US, CA, Santa Clara

… testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology …

Added Oct 27, 2026

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Nvidia

Senior DFT - Silicon Validation Engineer

US, CA, Santa Clara

… Our latest innovations support progress in AI. We keep evolving to solve emerging challenges. As a Senior DFT - Silicon Validation Engineer, you will work on ground breaking technologies in DFT to accelerate and …

Added Oct 27, 2026

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Intel

Senior DFT Logic Design Engineer

US, Arizona, Phoenix +2 locations

Pay posted by employer$141,910–$269,100 USD per year

… design packages. Come join us and do something wonderful. The Aerospace, Defense, Government (ADG) - The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, …

Added Oct 27, 2026

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Nvidia

Senior Circuit Silicon Correlation DFT Engineer

India, Bengaluru

… RAM types, chips and processes and improve correlation in the long run Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM. What we need to see: …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design Own …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States +1 location

Pay posted by employer$167,700–$245,200

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan …

Added Oct 28, 2026

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Nvidia

Senior DFT Methodology - Data Analytics and Applied AI Engineer

US, CA, Santa Clara

Added Oct 29, 2026

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Boeing

ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$119,850–$162,150

… tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners. Position Responsibilities: Design and implement DFT architectures and test …

Added Oct 12, 2026

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Nvidia

Senior JTAG Methodology Engineer

US, CA, Santa Clara

We are now looking for a Senior JTAG Methodology Engineer! As a Senior JTAG Methodology Engineer, you will architect and develop the test …

Added Oct 27, 2026

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Intel

Senior ASIC Verification Engineer

Israel, Haifa

… flow — planning, stimulus and checker development, coverage analysis, debug and more — and we look to our senior verification engineers to help steer that evolution. If you are energized by defining things that have …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

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About this opportunity

Original employer description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products.
You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others
As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc.
Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations teams to productize new methodologies
Help the team with delivering efficient workflows and tools to help productize these features on industry's leading processors for deep learning, gaming, HPC and supercomputing
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

BSEE (or equivalent experience) with 8+ years, MSEE with 5+ years of experience or PhD with 3+yrs in DFT or related domains
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired
Extraordinary written and oral communication skills with the curiosity to work on rare challenges

Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, but it is also energy efficient! We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 26, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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