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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Austin, Texas, United States +2 locations
Pay posted by employer$143,800–$230,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
Austin, Texas, United States +2 locations
Pay posted by employer$121,900–$195,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
Malaysia, Penang +1 location
The Role and Impact As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom …
McKinney, Texas, United States
… missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production …
Santa Clara, California, United States +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
Westborough, MA +1 location
… with industry-leading packaging techniques. What You Can Expect As a Signal and Power Integrity Engineer in the Advanced Packaging design team, you will be responsible for the following: SI/PI analysis of designs …
Caesarea, Israel
… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …
San Jose, California, United States +1 location
Pay posted by employer$121,900–$195,000 USD per year
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to …
Santa Clara, California, United States +2 locations
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. …
USA - Mountain View, CA
Pay posted by employer$119,850–$162,150
. You will work on leading‑edge ASICs used in space and aerospace systems—driving architecture, verification, tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, …
Santa Clara, California, United States
We are now looking for a Senior Mixed Signal Design Engineer to be part of the Mixed Signal design team building next generation NVLINK. This position offers …
Caesarea, Israel
You'll be joining our Physical Design team at Cisco Silicon One, which is at the center of the silicon development at Cisco. Our engineers deal …
Malaysia, Penang
… team is looking for a highly motivated and technically savvy experienced individual to join our team as Design Automation Engineer. Intel has a vision to create and extend computing technology to connect and enrich the …
MIL - Be'er Sheva Negev Park - Office
Micron Technology seeks an RTL design engineer to develop digital blocks from specification through RTL implementation with strong emphasis on …
Santa Clara, California, United States
… In this role you’ll be a member of the Data Center Engineering business group. Our group owns the digital design of high performance mixed signal ICs used in high speed interconnects in hyperscaler data centers. These …
Singapore, Singapore
… its capabilities in automated, connected and AI-enabled laboratory workflows. We are seeking a Staff Engineer in Laboratory Automation & Systems Integration to develop solutions connecting GSD instruments and …
Portage, Michigan, United States
Pay posted by employer$89,300–$148,800 USD
… meet quality requirements for safety and effectiveness. Support the collection of market feedback to inform design requirements and validate the design with customers as it matures through the production launch. Work …
Hillsboro, Oregon, United States
Pay posted by employer$122,440–$172,860 USD per year
… leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for …
USA - Berkeley, MO
Pay posted by employer$129,200–$174,800
Include: Lead major design activities for hardware/software products Mentor junior engineers in design practices and processes; …
Stafford, England, United Kingdom
… Control & Protection, and Product Care function reporting directly to the Head of Control and Protection Verification & Validation. This role includes developing department talent, engineering process management, provide …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
