264 matching jobs for “SoC Design Verification Engineer”

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Intel

Chassis IP Design Engineer

Bengaluru, Karnataka, India

The Role and Impact As an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP …

Added Oct 27, 2026

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Broadcom

Lead Physical Design Engineer

IND-Pune EON Kharadi Infrastructure

Full time
Regular

Role Overview As a Lead Physical Design Engineer, you will drive physical design implementation for complex SoC architectures on 5nm and advanced …

Added Oct 27, 2026

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Broadcom

Design Engineer - STA

Fort Collins, Colorado, United States

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …

Added Oct 5, 2026

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Cisco Systems

… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design …

Added Oct 27, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

The Role and Impact As a DFT Design Engineer, you will play a crucial role in developing and delivering high-quality design-for-test (DFT) …

Added Nov 3, 2026

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Nvidia

CPU Design Methodology Engineer

Hillsboro, Oregon, United States +3 locations

We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now …

Added Oct 27, 2026

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Senior ASIC Design Engineer

Vancouver, Washington, United States

Full time
Reg Employee

Pay posted by employer$116,150–$182,400 USD per year

Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification. …

Added Oct 12, 2026

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Nvidia

Senior ASIC Design Engineer

Santa Clara, California, United States

will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor …

Added Oct 27, 2026

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Nvidia

ASIC Verification Engineer - New College Grad 2027

Austin, Texas, United States +1 location

… join the team and see how we can make a lasting impact on the world! NVIDIA is seeking an outstanding ASIC Verification Engineer - New College Graduate to verify the design and implementation of the world’s leading SoC's and …

Added Oct 27, 2026

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Nvidia

ASIC Design Engineer - Hardware

Austin, Texas, United States

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and …

Added Oct 27, 2026

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Analog Devices

Senior Digital Design Engineer

Bengaluru, Karnataka, India +1 location

… & Scope, Business Impact). Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using …

Added Nov 3, 2026

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Intel

Senior DFT Design Engineer

Folsom, California, United States +3 locations

Pay posted by employer$141,910–$172,860 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Nov 4, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

GPU Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Intel

GPU Logic Design Engineer

Santa Clara, California, United States +1 location

Pay posted by employer$105,650–$200,340 USD per year

As a GPU Logic Design Engineer, you will play a vital role in developing cutting-edge graphics IPs required for next-generation …

Added Oct 27, 2026

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Nvidia

Formal Verification Engineer - New College Grad 2026

Santa Clara, California, United States

… on the world. NVIDIA is looking for sharp, curious, and motivated students who are passionate about formal verification, digital design, and computer architecture. In this role, you will help verify advanced processor and …

Added Oct 27, 2026

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Nvidia

Senior Digital Design Engineer

Santa Clara, California, United States +2 locations

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard …

Added Oct 31, 2026

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Cisco Systems

Senior RTL Design Engineer

Armenia

… the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and …

Added Oct 27, 2026

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Broadcom

Memory Layout Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

… knowledge. Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules). Strong layout knowledge in advanced submicron FinFET processes, including …

Added Oct 5, 2026

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Nvidia

Senior Verification Engineer – High Speed Coherent Interconnect Hub

Toronto, Ontario, Canada

NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

Santa Clara, California, United States

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This …

Added Oct 27, 2026

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Intel

Chassis IP Design Engineer

Bengaluru, Karnataka, India

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Qualifications · employer excerpt

Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of experience in state-of-the-art SoC or IP design OR Master's degree with 3+ years of experience.- Proficiency…

About this opportunity

Original employer description

Job Details:

Job Description:

The Role and Impact
As an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP blocks that drive Intel's cutting-edge SoC solutions. Your day-to-day responsibilities will include writing register transfer level (RTL) code, conducting simulations, and ensuring designs meet stringent power, performance, area, and timing goals. You'll play a pivotal role in delivering quality IPs while collaborating across architecture, verification, and SoC integration teams to ensure seamless handoffs and impactful results.

Business group
The Central Engineering Group (CEG) is Intel's leading innovation hub, focused on designing foundational technologies for integration across Intel's product portfolio. Within this team, the UIC Fabric Design organization specializes in developing reusable IP blocks and subsystems that enhance system-level capabilities. This group contributes to Intel's broader mission of delivering world-class solutions to revolutionize computing across industries.

Key Responsibilities
- Design and develop RTL code for IP blocks, ensuring functionality, quality, and scalability.
- Optimize logic designs to meet power, performance, area, and timing objectives.
- Collaborate with architecture teams to define microarchitecture features of IP designs.
- Participate in verification plan reviews and implement corrective measures for failing RTL tests.
- Support SoC integration teams to ensure high-quality integration and verification of IP blocks.
- Work with physical design teams to address timing and implementation challenges.
- Drive compliance with quality assurance standards for seamless IP-SoC handoff.

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of experience in state-of-the-art SoC or IP design OR Master's degree with 3+ years of experience.
- Proficiency in Verilog/System Verilog, including Lint/CDC/RDC tools and methodologies.
- Demonstrated ability to optimize designs for power, performance, and area trade-offs (PPA).

Preferred Qualifications
- Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.
- Experience in designing IP subsystems, including protocol conversion bridges and debug/trace components.
- Understanding of concepts such as QoS, access control, flow control, RAS, and security/error handling.
- Proven ability to collaborate across architecture, verification, and SoC integration teams effectively.
- Familiarity with using AI tools to assist logic design.
- Strong communication skills and experience working with globally distributed teams across time zones.

We invite you to join our team, where you'll be empowered to innovate, collaborate, and leave a lasting impact on the future of computing.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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