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Bengaluru, India
Develop and implement verification plans and test benches using Simulation tools and methodologies. Collaborate with design and validation …
Bengaluru, India
We are looking for a talented and motivated Layout Engineer to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical …
US, CA, Santa Clara +1 location
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
Responsibilities: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these …
Vancouver, Washington, United States
Pay posted by employer$116,150–$182,400 USD per year
Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification. Proactively work with other …
US, CA, Santa Clara
will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. In addition to the design role, you will …
Fort Collins, Colorado, United States
Pay posted by employer$129,400–$207,000 USD per year
Broadcom’s ASIC Products Division is seeking a Design Automation Software Development Engineer. They will define, develop, …
US, CA, Santa Clara +4 locations
NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world’s most powerful AI-enabled SoCs. These SoCs power self-driving …
San Jose, California, United States
Pay posted by employer$155,000–$222,600
… users. Support releases, tool qualification, and regression signoff. Collaborate with DFT Design, ATPG, Verification, Physical Design, and CAD teams. Minimum Qualifications: Bachelor’s degree in Electrical or Computer …
US, CA, Santa Clara
We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. …
China, Shanghai
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: …
US, CA, Santa Clara +1 location
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the …
Office - USA - CA - Headquarters
About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own …
Office - USA - CA - Headquarters
Your Career As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …
Caesarea, Israel
Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow …
Armenia
We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You …
Israel, Tel Aviv +1 location
… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …
Armenia
… and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure …
Belgrade, Serbia
Meet the Team Join our SiliconOne team in Serbia, specializing in ASIC functional verification for Cisco Silicon One chips—high-performance networking chips utilized by major …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
