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US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… and defense. We are seeking an experienced and highly motivated Senior Principal Electrical or Computer Engineer to support the design, development, and integration of advanced digital ASIC and FPGA solutions for …
Cedar Rapids, Iowa, United States
… Join us and help shape the future of aerospace and defense. We are hiring a Senior Principal Electrical Engineer (P5) for our growing Avionics FPGA/ASIC team in Cedar Rapids, IA. This position is for a highly experienced …
Carlsbad, California, United States +1 location
Pay posted by employer$192,400–$275,800
… Cisco’s industry-defining Silicon One Optics group, you won’t just follow the future of networking—you’ll engineer it. We are actively building the hyper-scalable optical transceivers and modules (800G, 1.6T, and beyond) …
Bengaluru, Karnataka, India
NVIDIA is seeking a highly enthusiastic and motivated Design Engineer to design and implement the next generation of control subsystems for the world’s leading GPUs. This …
Folsom, California, United States +3 locations
Pay posted by employer$220,920–$311,890 USD per year
… driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs …
Hsinchu, Taiwan, Taiwan +1 location
• Test Architecture & Development: Drive test program development and verification on automated test equipment (Advantest V93000 / SmarTest 7 & SmarTest 8) across digital, high-speed SerDes, …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… Join us to power the future of the digital world. Your Impact: In this role as a Post-Silicon Validation Engineer, you will be responsible for: Planning and setting up Silicon Bring-up infrastructure, including system …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
Verification environment architecture and design using SystemVerilog with OVM/UVM Creation of written test plan, …
China, Shanghai
… of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, …
Bengaluru, Karnataka, India
… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System …
Toronto, Ontario, Canada
NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… the future of the digital world. Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep …
Santa Clara, California, United States
NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum Qualifications Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or …
San Jose, California, United States +1 location
Pay posted by employer$167,700–$245,200
… ATE screening, in-system test, debug and diagnostics needs of the design Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation …
Armenia
… ATE screening, in-system testing, debugging, and diagnostics. We collaborate closely with design, design-verification, and product development teams to integrate and validate test logic throughout implementation and …
Bengaluru, Karnataka, India +1 location
… power management architecture of next generation chips. One should possess strong digital design and verification fundamentals. What you'll be doing: As a designer, be responsible for making architectural trade-offs based …
Santa Clara, California, United States
… the team and see how we can make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly grow the research and development of …
San Jose, California, United States +2 locations
Pay posted by employer$143,800–$230,000 per year
Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …
San Jose, California, United States +2 locations
Pay posted by employer$143,800–$230,000 per year
Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
