Cisco Systems
Senior Asic Design - Cisco Silicon One
Caesarea, Israel
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ASIC Engineer · AnywhereEdit
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621 matching jobs for “ASIC Engineer”
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Boeing
ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)
USA - Mountain View, CA
- In person
- Full time
- Regular
Pay posted by employer$98,600–$133,400
ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: …
Cisco Systems
ASIC High Speed AMS Technical Leader
Carlsbad, California, United States +1 location
Pay posted by employer$192,400–$275,800
… Your Impact Build the optical backbone of the AI revolution. As our High-Speed Analog/Mixed-Signal Design Engineer, you will directly lead the electrical specifications, custom circuit design, and verification strategies …
Marvell Technology
Sr. Staff CAD- ASIC Design Verification Agentic Workflow
Santa Clara, California, United States
- Regular
… design infrastructure, methodology and workflows. What You Can Expect We are seeking a highly innovative engineer to lead the development of next-generation Agentic AI workflows for Front-End Engineering. This role will …
Cisco Systems
ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years
Bengaluru, Karnataka, India +1 location
… requires the candidate to have the ability to craft solutions and debug with minimal mentorship. You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of …
Cisco Systems
ASIC Design Verification Engineer | Simulation & Emulation , Test methodologies | 7 to 11 Years | Bangalore
Bengaluru, Karnataka, India
Boeing
ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)
USA - Mountain View, CA
- In person
- Full time
- Regular
Pay posted by employer$119,850–$162,150
… How to make your application stand out : Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g., achieved timing closure on X‑nm blocks, …
Cisco Systems
Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)
San Jose, California, United States +5 locations
Pay posted by employer$186,900–$267,700
… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …
Cisco Systems
Hardware ASIC Packaging SI/PI Simulation and Design Lead (Hybrid)
San Jose, California, United States +10 locations
Pay posted by employer$186,900–$267,700
… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …
Cisco Systems
ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Exp 4 to 8 years
Bengaluru, Karnataka, India +2 locations
Cisco Systems
ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years
Bengaluru, Karnataka, India +1 location
Cisco Systems
ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years
Bengaluru, Karnataka, India
… and efficient performance. • Support testing of design in emulation. • Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications • Bachelor’s degree or master’s Degree in equivalent experience in …
Cisco Systems
Principal Hardware Systems Architect - ASIC (Silicon One) Ecosystem Integration & Product Strategy (Hybrid)
San Jose, California, United States
Pay posted by employer$233,900–$330,400
… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …
Cisco Systems
ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore
Bengaluru, Karnataka, India +1 location
… being developed in the industry. Your Impact: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL …
Cisco Systems
DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore
Bengaluru, Karnataka, India
Cisco Systems
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Pune, Maharashtra, India
… including AI/ML workloads, and next-generation data center architectures. Your Impact As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you …
Cisco Systems
Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years
Bengaluru, Karnataka, India
… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System …
Cisco Systems
ASIC DFT Technical Leader || MBIST, SCAN , ATPG, Testmax, Tessent, Post Silicon Validation || Expereince - 11+ years
Bengaluru, Karnataka, India +1 location
… developed in the industry. Your Impact : You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL …
Cisco Systems
ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore)
Pune, Maharashtra, India +1 location
… outcomes for 100G, 200G, and 400G optical interconnects. This role involves managing the full ASIC lifecycle, from architectural conception and RTL-based design of CPU subsystems and data path interfaces to …
Cisco Systems
ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs | 12-16 Years | Pune/ Bangalore)
Pune, Maharashtra, India +1 location
… outcomes for 100G, 200G, and 400G optical interconnects. This role involves managing the full ASIC lifecycle, from architectural conception and RTL-based design of CPU subsystems and data path interfaces to …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.