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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
McKinney, Texas, United States
… Identify and manage project risks and opportunities. Create complete documentation including requirements, verification plan, and user’s guides Lead medium sized teams to success. Coach, review, and delegate work to junior …
San Jose, California, United States
Pay posted by employer$82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
San Jose, California, United States
Pay posted by employer$82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
Bengaluru, Karnataka, India
… fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from …
Bengaluru, Karnataka, India
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for …
Tel Aviv, Tel Aviv, Israel
… and enterprise networks. Cisco's silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large …
McKinney, Texas, United States
… Concept of Operations (CONOPS). Design and code in VHDL for reliability and maintainability. Support design verification utilizing self-checking techniques with directed and constrained random tests, while tracking functional …
Irvine, California, United States
ASIC Verification Engineer High Speed Interconnect Product (HSIP) Group The Opportunity Broadcom is the global leader in semiconductor …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, …
Armenia
… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… architecture and design through production and sustainment. The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
Bengaluru, Karnataka, India
… position requires a breadth of disciplines and responsibilities in supporting the Processor based subsystem verification for the ‘ASIC Products Division’ within Broadcom Limited. Responsibilities will include Verification …
San Jose, California, United States +3 locations
Pay posted by employer$121,900–$195,000 USD per year
… partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies to achieve desired PPA metrics. Candidate would …
Hillsboro, Oregon, United States +3 locations
We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of …
Santa Clara, California, United States
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… and design through production and sustainment. The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
US-CA-San Jose, California +1 location
Job Description What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT …
Malaysia, Penang
… talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing …
Santa Clara, California, United States +2 locations
We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working …
Israel, Yokneam +1 location
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
