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Malaysia, Penang
… talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing …
Israel, Yokneam +1 location
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are …
Santa Clara, California, United States +2 locations
We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working …
Bengaluru, Karnataka, India +1 location 3 postings
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
IND-Pune EON Kharadi Infrastructure
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India 2 postings
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Israel, Yokneam
NVIDIA Analog Layout design team is looking for a Senior Analog Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenge …
Bengaluru, Karnataka, India
GPU Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media …
Tucson, Arizona, United States
… over the world, from the ground to exoatmospheric environments and into space. As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …
Santa Clara, California, United States +1 location
… adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for …
Marlborough, Massachusetts, United States
Requirements capture, FPGA digital architecture and design using RTL, timing closure, verification, and system integration Optimize FPGA implementations to meet performance, power, and size constraints. …
San Jose, California, United States +3 locations
Pay posted by employer$143,800–$230,000 USD per year
… partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Drive tools and methodologies to achieve desired PPA metrics. Complete equivalence checks, STA, …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… from architecture and design through production and sustainment. The MPD department is seeking an FPGA Engineer II to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
Bengaluru, Karnataka, India
The Role and Impact: As a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly to the …
China-Shanghai-Zhangjiang Hi Tech
… customers to develop state of the art IC solutions utilizing Broadcom's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… more, and work quickly. Join us to power the future of the digital world. Your Impact Develop and maintain ASIC APIs and SDKs in C and C++, delivering clean, scalable updates that support emulation, bring-up, and …
Bengaluru, Karnataka, India +1 location
… analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust …
Melbourne, Florida, United States
… market. Join us and help shape the future of aerospace and defense. Collins Aerospace is seeking a FPGA Engineer II for the CNS (Communication, Navigation, Surveillance) Hardware Engineering Group in Melbourne, Florida. …
Irvine, California, United States +1 location
… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
