1,000+ matching jobs for “Physical Design Engineer”

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Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Intel

Design Automation Engineer - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Pay posted by employer$122,440–$232,190 USD per year

… new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the …

Added Oct 27, 2026

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Analog Devices

Staff Mixed-Signal Design Engineer

Newbury, England, United Kingdom +4 locations

As a Staff Mixed Signal Design Engineer, you will provide technical leadership in the design and development of sophisticated mixed-signal …

Added Nov 3, 2026

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Nvidia

Senior ASIC Floorplan Design Engineer

Santa Clara, California, United States +1 location

We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading …

Added Oct 31, 2026

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Analog Devices

Staff Engineer, Design Verification Engineering

Bengaluru, Karnataka, India

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification …

Added Nov 3, 2026

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Broadcom

Staff Memory Circuit Design Engineer

USA-Mendota Heights-Northland

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Staff Memory Circuit Design Engineer We are looking for energetic and passionate memory design engineers to join our Central …

Added Oct 5, 2026

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Analog Devices

Senior Engineer, Analog Design Engineering

Taiwan, Taipei, Songgao

ADI Taipei Design Center is seeking an experienced Senior Analog IC Design Engineer to support assigned IC products through …

Added Nov 3, 2026

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Broadcom

Staff Memory Circuit Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the …

Added Oct 5, 2026

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Cisco Systems

Hardware Engineer- HW Board Design

Caesarea, Israel

Cisco Silicon One is seeking a HW Board Design Engineer. Meet the Team Our Board Design Team is growing! You’ll collaborate with top industry engineers …

Added Oct 27, 2026

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GE Vernova

Lead Civil Engineer - Structural Design

Queretaro

Summary Lead Civil/Structural engineer designing electrical high voltage substations is a technical leader across the engineering teams who leads …

Added Oct 27, 2026

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Intel

Principal Engineer- CPU Circuit Design

Bengaluru, Karnataka, India

The Role and Impact As CPU Circuit Design Lead, you will lead the development of advanced digital circuits for custom blocks such as SRAM, register …

Added Oct 27, 2026

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Nvidia

Senior Mask Layout Design Engineer

Hsinchu, Taiwan, Taiwan +1 location

… is our life’s work, to amplify human creativity and intelligence. We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for …

Added Oct 27, 2026

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Marvell Technology

Package Design Quality Assurance Engineer

Burlington, Vermont, United States

Regular

… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging Design team is responsible for supporting customers with package solutions that meet challenging electrical …

Added Nov 3, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States +1 location

… to the world. This is our life’s work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, …

Added Oct 31, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States

Are you a Mask Layout Design Engineer? We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing …

Added Oct 31, 2026

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Analog Devices

Senior Engineer, Design Evaluation Engineering

Cavite City, Calabarzon, Philippines

… testing, failure analysis, root cause investigation, and corrective action implementation. Electronic Design : Expert-level capabilities in complex electronic component design Mechanical/Optical Systems : …

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Digital Design Engineering

China, Beijing, Haidian, Xixiaokou

… definition, RTL development, synthesis, timing closure, DFT collaboration, and close partnership with physical design teams to deliver robust, production‑ready designs. Key Responsibilities: Define and develop …

Added Nov 3, 2026

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R&D Mechanical Design Engineer

Singapore, Singapore

Full time
Reg Employee

… The role contributes to process efficiencies and resolves challenges. Responsibilities Deliver product design & assemblies to production on time, cost and to specification (functionality, reliability, safety & …

Added Oct 12, 2026

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Nvidia

Senior Mask Layout Design Engineer

Santa Clara, California, United States +1 location

… and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers. Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, …

Added Oct 31, 2026

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Marvell Technology

Senior Staff Hardware Design Engineer

Irvine, California, United States

Full time
Regular

… evaluation platforms that demonstrate performance and accelerate customer adoption. As a Sr. Staff Hardware Design Engineer, you’ll work at the intersection of high-speed electronics, optical communications, and system …

Added Nov 3, 2026

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Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

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Minimum Qualifications · employer excerpt

Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
Experience in System Verilog, UVM, and verification methodologies.
Experience architecting verification strategies for complex ASIC programs.
Experience leading verification teams or projects.
Experience in scripting (Python, Perl) and C/C++ programming language.

About this opportunity

Original employer description

The application window is expected to close on: 11/29/2026

This role requires being onsite in San Jose, CA at least 4 days/week.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Set vision and strategy for ASIC verification methodology and execution across multiple programs and product lines.
Serve as technical authority and mentor for verification teams, fostering technical excellence and innovation.
Lead architecture and implementation of scalable, reusable verification infrastructure and methodologies.
Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
Influence ASIC architecture and design to enable robust verification and high-quality silicon.
Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.
Provide technical leadership in root cause analysis and resolution of complex issues during bring-up and post-silicon validation.

Minimum Qualifications

Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
Experience in System Verilog, UVM, and verification methodologies.
Experience architecting verification strategies for complex ASIC programs.
Experience leading verification teams or projects.
Experience in scripting (Python, Perl) and C/C++ programming language.

Preferred Qualifications

Experience in data center, Hyperscalers, or AI Networking technologies.
Author or contributor to industry standards or best practices in ASIC verification.
Deep expertise in multiple protocols and large-scale SoC architectures.
Experience with advanced emulation, prototyping, and formal verification tools at scale.
Experience with silicon bring-up and post-silicon debug.
Strong leadership, communication, and mentoring skills.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$167,700.00 - $282,000.00

Non-Metro New York state & Washington state:

$149,100.00 - $250,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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