635 matching jobs for “ASIC Design Engineer”

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RTX

Principal FPGA Engineer

McKinney, Texas, United States

… a minimum of 8 years of prior relevant experience. Experience to include one or more of the following: FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding) Experience with AMD …

Added Oct 27, 2026

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Cisco Systems

Senior Modeling Software Engineer

Tel Aviv, Tel Aviv, Israel

… and enterprise networks. Cisco's silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large …

Added Oct 27, 2026

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Broadcom

Verification Engineer

San Jose, California, United States +1 location

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

Broadcom’s ASIC Product Division (APD) is focused on enabling customers to develop products with a sustainable and …

Added Oct 5, 2026

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Leidos Holdings

FPGA Engineer

San Diego, California, United States

Pay posted by employer$87,100–$157,450

… execute FPGA test plans, determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA performance. Support electrical engineering activities including FPGA designs and …

Added Nov 3, 2026

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Cisco Systems

Software Engineer

Caesarea, Israel

Cisco Silicon one is seeking a highly motivated and experienced Software Engineer for a position focused on developing innovative network device monitoring and visualization solution. Meet …

Added Oct 27, 2026

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Nvidia

Firmware Engineer - Ethernet Switching

Ra'anana, Central District, Israel

… on the most groundbreaking technologies. NVIDIA’s Networking BU group is seeking to hire an expert Firmware Design Engineer for the Ethernet Switch Firmware Core team. The next generation of Switches are a crucial …

Added Oct 27, 2026

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Cisco Systems

Senior C++ Software Engineer

Caesarea, Israel +1 location

… and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization …

Added Oct 27, 2026

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RTX

FPGA ENGINEER II

McKinney, Texas, United States

… development of FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS). Design and code in VHDL for reliability and maintainability. Support design verification utilizing self-checking …

Added Oct 27, 2026

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Nvidia

DFT Engineer - Hardware

Bengaluru, Karnataka, India

… that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions …

Added Oct 27, 2026

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Nvidia

Physical Verification Engineer

Israel, Tel Aviv +1 location

NVIDIA is seeking a Physical Verification Engineer to help ensure our ASIC and SoC designs are clean, correct, and ready for tapeout. This role focuses on …

Added Oct 27, 2026

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Nvidia

Senior Memory System Engineer

Santa Clara, California, United States

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of …

Added Oct 27, 2026

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Intel

Senior Verification Engineer

Leixlip, Leinster, Ireland

Full time
Regular

The Role and Impact You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As a senior IP Design …

Added Oct 27, 2026

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Nvidia

Formal Verification Engineer

China, Shanghai

… The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions …

Added Oct 27, 2026

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Broadcom

Principal Physical Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — …

Added Oct 25, 2026

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Broadcom

Principal Mechanical Engineer

Ottawa March Road

Full time
Regular

Pay posted by employer$114,400–$183,000 CAD per year

As a Principal Mechanical Engineer, you will design, develop, and deliver Mechanical assemblies, including full chassis design for Ultra …

Added Oct 9, 2026

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Broadcom

Principal Hardware Engineer

Ottawa March Road 2 postings

Full time
Regular

Pay posted by employer$114,400–$183,000 CAD per year

As a Principal Hardware Engineer, you will design, develop, and deliver Ultra High-performance electronic products. In addition, you may …

Added Oct 28, 2026

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Broadcom

Senior Hardware Engineer

Ottawa March Road

Full time
Regular

Pay posted by employer$76,300–$122,000 CAD per year

As a Senior Hardware Engineer, you will design, develop, and deliver Ultra High-performance electronic products. In addition, you may …

Added Oct 21, 2026

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Broadcom

Staff Hardware Engineer

Ottawa March Road

Full time
Regular

As a Staff Hardware Engineer, you will be the technical lead responsible for a design team developing and delivering …

Added Oct 21, 2026

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Broadcom

Staff Hardware Engineer

Ottawa March Road

Full time
Regular

As a Staff Hardware Engineer, you will be the technical lead responsible for a design team developing and delivering …

Added Oct 21, 2026

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Broadcom

Principal Hardware Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

As a Principal Hardware Engineer, you will be the technical lead responsible for a design team developing and delivering …

Added Oct 9, 2026

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RTX

Principal FPGA Engineer

McKinney, Texas, United States

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About this opportunity

Original employer description

Date Posted:

2026-09-24



Country:

United States of America



Location:

US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG



Position Role Type:

Onsite



U.S. Citizen, U.S. Person, or Immigration Status Requirements:

The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance



Security Clearance Type:

DoD Clearance: Secret



Security Clearance Status:

Active and existing security clearance required after day 1

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.

We are currently seeking a Principal Electrical Engineer, with strong technical leadership ability, to function as the Field Programmable Gate Array Lead.

This position is an onsite role, located in McKinney, TX.

What you will do

Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
Generate FPGA designs for the following applications: gigabit and multigigabit transceiver (MGT) serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
Translate system level requirements into FPGA requirements
Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
Lead small teams of FPGA engineers and code in VHDL for reliability and maintainability
Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
Identify and manage project risks and opportunities.
Create complete documentation including requirements, verification plan, and user’s guides
Lead medium sized teams to success.
Coach, review, and delegate work to junior engineers.
Serve as a subject-matter expert within discipline.
Lead internal and external technical reviews.
Support customer interactions and relations.
Contribute to product and technology roadmaps
Make improvements to processes, systems or products to enhance overall performance
Engage in personal technical growth and facilitate technical growth in peers and junior engineers.

Qualifications You Must Have

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience.
Experience to include one or more of the following:
- FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
- Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
- Hands on experience with integration and debug of FPGA/ASIC in a lab environment
- Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
- Experience with source code management, design reviews, and code release in a team development environment.

Qualifications We Value

One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.
FPGA/ASIC design experience in one or more of the following areas:
- Radar processing techniques
- Image processing techniques for visual and infrared sensors
- Embedded systems design using ARM, Microblaze, or NIOS processors
- Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
- Constrained random verification in UVM using System Verilog
- Verification utilizing emulation platforms, such as Veloce
- Experience with High Level Synthesis (HLS)
- Experience with vector processors and/or GPUs
- Using AI to improve FPGA workflows (verification automation, log triage, regression analytics)
- AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators)
Demonstrated ability to lead successful teams.
Experience managing technical, cost, and schedule risks and opportunities.
Experience with project management tools such as Earned Value and/or Agile Execution.
Experience communicating and documenting technical topics and presenting to customers and management.
Experience leading a program transition from development to production.
Proposal development experience.
Experience with intellectual property generation (patents & publications).
Demonstrated mentorship of junior engineers.

What We Offer

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.

This position offers relocation based on candidate eligibility.

Learn More & Apply Now!

This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website

here: https://www.state.gov/m/ds/clearances/c10978.htm

gov/m/ds/clearances/c10978.htm

North Texas: https://careers.rtx.com/global/en/raytheon-north-texas-location

#LI-CV1

As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.

The salary range for this role is 107,500 USD - 204,500 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.

Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.

Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.

This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.

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