ASIC Engineer · AnywhereEdit
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544 matching jobs for “ASIC Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$155,000–$222,600

… experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center …

Added Oct 27, 2026

Nvidia

Senior ASIC Verification Engineer

US, TX, Austin

… human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an experienced ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at …

Added Oct 27, 2026

Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… and work quickly. Join us to power the future of the digital world. Your Impact Set vision and strategy for ASIC verification methodology and execution across multiple programs and product lines. Serve as technical …

Added Oct 27, 2026

Cisco Systems

ASIC Physical Design Engineer

Armenia

… degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably …

Added Oct 27, 2026

Cisco Systems

PHY Algo ASIC Engineer

Tel Aviv, Israel +1 location

… implementation feasibility. Support Hardware & Software Integration: Collaborate closely with digital ASIC design, firmware, and systems engineering teams to ensure accurate fixed-point translation and RTL …

Added Oct 29, 2026

Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

  • Full time
  • Regular

Pay posted by employer$143,800–$230,000 per year

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be …

Added Oct 5, 2026

Broadcom

ASIC Package Design Engineer

San Jose, California, United States +2 locations

  • Full time
  • Regular

Pay posted by employer$143,800–$230,000 USD per year

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power …

Added Oct 20, 2026

Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… more, and work quickly. Join us to power the future of the digital world. Your Impact Participate in the ASIC design verification for Cisco high-end switching products. Perform end-to-end verification of design blocks …

Added Oct 27, 2026

Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$155,000–$222,600

… experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center …

Added Oct 27, 2026

Nvidia

Senior ASIC Timing Engineer

US, CA, Santa Clara +3 locations

… join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of …

Added Oct 27, 2026

Cisco Systems

ASIC DFT STA Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… the future of the digital world. Your Impact: You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep …

Added Oct 27, 2026

RTX

FPGA/ASIC Engineer II (Onsite)

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

You will support requirements capture and ASIC / FPGA digital architecture. You will implement ASIC / FPGA digital design using RTL. You will support …

Added Oct 27, 2026

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.

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