Physical Design Engineer · AnywhereEdit
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1,000+ matching jobs for “Physical Design Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

System Hardware Board Design Engineering Lead (Onsite)

Milpitas, California, United States

Pay posted by employer$171,600–$245,000

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

Cisco Systems

Advanced Packaging Design Engineering Team Lead (Hybrid)

San Jose, California, United States

Pay posted by employer$186,900–$267,700

… portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for …

Added Oct 30, 2026

Marvell Technology

Ph.D. Intern - AI/ML & Design Automation

Santa Clara, California, United States +8 locations

  • Full time
  • Internship

… the AI era demands requires more than engineering talent. It requires intelligence applied to the design process itself. Marvell's AI and machine learning teams are working on exactly that — using AI to …

Added Nov 3, 2026

Cisco Systems

Advanced Packaging Design Engineering Team Leader (Hybrid)

San Jose, California, United States

Pay posted by employer$214,100–$309,800

… portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for …

Added Oct 27, 2026

Marvell Technology

Ph.D. Intern - Analog, Mixed Signal & Circuit Design

Santa Clara, California, United States +2 locations

  • Full time
  • Internship

… link, analog and mixed-signal circuits are doing the work that makes it possible. At Marvell, our analog design team is the reason those circuits exist. The custom XPUs, the 224G and 448G SerDes IP, the Silicon …

Added Nov 3, 2026

Marvell Technology

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Santa Clara, California, United States

  • Regular

… member of Marvell Central Engineering, you will play a leading role on developing next-generation Agentic design verification workflow and its add-on tools. You will have the opportunity to use your extensive design and …

Added Nov 3, 2026

Intel

Director - Intel Foundry Pre-Silicon Design Quality and Reliability

Hillsboro, Oregon, United States +1 location

  • Full time
  • Regular

Pay posted by employer$271,620–$383,460 USD per year

… leader of Intel's Foundry pre-Silicon Quality and Reliability team, you will lead a high-performing team of Design and Quality and Reliability engineers responsible for the tools and flows which allow Foundry customers to …

Added Oct 27, 2026

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.

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