Searching jobs…
Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Santa Clara, California, United States
… reliability, silicon operations, manufacturing, and collaborators outside the company to ensure strong design-to-test alignment. Lead the strategy for ATE platform selection, vendor engagement, capacity readiness, and …
Adliswil, Zurich, Switzerland
… electrical interfaces for next-generation optical engines (400G/lane CPO and beyond) Perform co-design across photonics, analog/ASIC design, and packaging teams to optimize performance, power efficiency, and …
Santa Clara, California, United States +1 location
… test engineering strategy, equipment/vendor selection, and manage test hardware suppliers Drive loadboard design strategy including schematic, layout, SI/PI, and simulation capabilities Manage NPI and production hardware …
Bengaluru, Karnataka, India
We are looking for a Principal System Software Architect to join our HW/SW Co-Design team. This is not a role about drawing abstract boxes on slides -- it is about making real, data-driven …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… a sufficient number of applications are received. Meet the Team Cisco Silicon One is the center of Cisco’s ASIC design and is driving the development of next-generation network devices for the AI/ML era. Our outstanding …
Santa Clara, California, United States
… and tooling: version planning, regression and quality gates, migration paths, and user adoption across design teams Collaborate with engineering teams to define requirements and document architecture, interfaces, and …
Malaysia, Penang +1 location
… hands-on training and development activities to enhance your technical and professional skills. Support the design, development, and implementation of innovative solutions. Contribute to a dynamic and inclusive work …
San Jose, California, United States
Pay posted by employer$171,600–$245,000
… connecting the large-scale compute infrastructure used for AI training and inference. We bring mechanical design and electronic hardware together across component, printed circuit board (PCB), and system interfaces, …
Milpitas, California, United States
Pay posted by employer$171,600–$245,000
will span from hardware definition to design, and from qualification to final product release to our customers. Designing the hardware for the Cisco …
Santa Clara, California, United States +1 location
Pay posted by employer$100,598–$100,602 USD per year
… internship focused on the future of AI inference and AI infrastructure with hardware/software co-design expertise. This internship approaches AI infrastructure as a hardware/software co-design challenge. The …
Kanata, Ontario, Canada +1 location
Pay posted by employer$147,400–$198,200
… You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia …
Kanata, Ontario, Canada
Pay posted by employer$223,100–$285,600
… You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the DSP ASIC. In addition, you will have the opportunity to interact with other …
Kanata, Ontario, Canada
Pay posted by employer$171,100–$216,300
… You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia …
El Segundo, California, United States
Pay posted by employer$99,000–$225,000
… Experience using Micro sof t Office tools Knowledge of Application-Specific Integrated Circuit ( ASIC ) chip design, FPGAs, and integration into ASICs Ability to communicate technical details with internal and …
El Segundo, California, United States
… Earned Value Management (EVM), and risk and opportunity management At least 5+ years experience with FPGA/ASIC development Qualifications We Prefer Strong communicator, able to interface with the spectrum of individual …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
