Senior Chip Design Engineer · AnywhereEdit
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625 matching jobs for “Senior Chip Design Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

Firmware Architect & Subsystem Technical Leader, Acacia

Maynard, Massachusetts, US

Pay posted by employer$192,400–$275,800

… architecture that configures, manages, and optimizes Acacia’s transceiver subsystems and future System-on-Chip (SOC) architectures. In this high-impact technical leadership role, you will: Lead end-to-end architecture, …

Added Oct 27, 2026

Applied Materials

Strategic Supply Chain Project Manager for New Products

Santa Clara, California, United States

Pay posted by employer$124,000–$171,000

… materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI …

Added Oct 27, 2026

Applied Materials

Product Management Director

Santa Clara, California, United States

Pay posted by employer$185,000–$254,000

… on critical complex issues that impact longer term product development and business success. Originate, design, perform, collect data, analyze and compile reports on unusually complex engineering experiments and …

Added Nov 10, 2026

Applied Materials

Director Pathfinding Solutions - Integrated Materials Solutions

Albany, New York, United States

Pay posted by employer$176,000–$242,000

… materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI …

Added Oct 27, 2026

Applied Materials

Process Integrator Advanced Packaging & Co-Packaged Optics R&D

Albany, New York, United States +1 location

Pay posted by employer$176,000–$242,000

… optical coupling and alignment, fiber attach interfaces, and advanced substrate or interposer integration. Design and execute structured experiments and DOEs to optimize optical loss, coupling efficiency, alignment …

Added Oct 27, 2026

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.

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