1,000+ matching jobs for “Senior Physical Design Engineer”

How results work

Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Intel

IP RTL Senior Design Engineer

India, Bangalore

The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified …

Added Oct 27, 2026

Save job

Broadcom

Senior Memory Circuit Design Engineer

Bengaluru, India

Full time
Regular

Analyze different memory architectures and highlight the tradeoffs Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design …

Added Oct 5, 2026

Save job

Cisco Systems

Senior ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

Save job

Baker Hughes

Senior Mechanical Design Engineer - Wellbore Construction

Houston, Texas, United States

Full time

Senior Mechanical Design Engineer – Wellbore Construction Do you enjoy executing evaluation and design of team …

Added Oct 27, 2026

Save job

Boeing

Senior Wire Design and Install Engineer

USA - El Segundo, CA

In person
Full time
Regular

Pay posted by employer$176,800–$239,200

Lead the design and qualification of wire harnesses for spaceflight applications, ensuring compliance with rigorous mission …

Added Oct 12, 2026

Save job

Boeing

Senior Structures Design Engineer – Wing & Empennage

USA - North Charleston, SC

In person
Full time
Regular

Pay posted by employer$129,600–$158,400

Develops, integrates and documents structural requirements to establish the wing and/or empennage design. Develops, maintains and modifies structural designs, using 3-D Computer Aided Design tools and/or other …

Added Oct 12, 2026

Save job

GE Aerospace

Senior Engineer - Military Preliminary Cycle Design

Evendale +1 location

Full time
Regular

Pay posted by employer$130,000–$173,000

Summary The Senior Engineer – Military Preliminary Cycle Design will work with Edison Works Project & Engineering to assess, …

Added Oct 27, 2026

Save job

Nvidia

Senior ASIC Design Engineer - Memory Subsystem

US, CA, Santa Clara

… work. Come join the team and see how we can make a lasting impact on the world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team! What you'll be doing : As a member of our Memory …

Added Oct 27, 2026

Save job

Intel

Design Verification Engineer

US, California, Santa Clara

Pay posted by employer$105,650–$149,150 USD per year

About Intel & Silicon Chassis Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification …

Added Oct 27, 2026

Save job

Boeing

Senior Electronic Design and Analysis Engineer

USA - El Segundo, CA

In person
Full time
Regular

… and develop high-level and detailed designs consistent with those requirements Guide structural design and configuration development by performing trade studies to optimize structure and meet program …

Added Oct 15, 2026

Save job

Nvidia

Senior ASIC Design Engineer - XBAR IP

India, Bengaluru

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem …

Added Oct 27, 2026

Save job

Boeing

Senior Electrical Design and Analysis Engineer

USA - Berkeley, MO

In person
Full time
Regular

Pay posted by employer$129,200–$174,800

Include: Lead major design activities for hardware/software products Mentor junior engineers in design practices and processes; …

Added Oct 12, 2026

Save job

Boeing

Experienced or Senior Digital Design Engineer

USA - Huntsville, AL

In person
Full time
Regular

Pay posted by employer$112,200–$151,800

Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and …

Added Oct 12, 2026

Save job

Boeing

Senior Mechanical Systems Design Analysis Engineer

USA - Hazelwood, MO

In person
Full time
Regular

Pay posted by employer$126,650–$171,350

Design and develop support equipment for military platform development and sustainment programs Create hardware …

Added Oct 15, 2026

Save job

Nvidia

Senior SOC Design Engineer - Networking Group

India, Bengaluru

We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll …

Added Oct 27, 2026

Save job

Boeing

Analog Design Engineer (Experienced or Senior)

USA - Huntsville, AL

In person
Full time
Regular

Pay posted by employer$112,200–$151,800

… and iterate designs. Research and evaluate emerging technologies and components; make recommendations for design improvements and technology investments to meet program needs. Produce clear technical documentation, …

Added Oct 12, 2026

Save job

Boeing

Structures & Payload Design Engineer (Payload Systems Design) - Experienced or Senior

USA - North Charleston, SC

In person
Full time
Regular

Pay posted by employer$103,700–$140,300

Structures & Payload Design Engineer (Payload Systems Design) - Experienced or Senior Company: The Boeing Company The Payloads …

Added Oct 12, 2026

Save job

Boeing

Design Engineer (Associate, Experienced, or Senior)

USA - El Segundo, CA

Full time
Regular

Pay posted by employer$90,950–$123,050

… Ground Support Equipment ( MGSE ) component designs using 3-D CAD tools (such as Creo Parametric) or other design methods, to provide product definition to other engineering groups, production operations, suppliers and …

Added Oct 14, 2026

Save job

Intel

Design Verification Engineer

US, California, Santa Clara +1 location

Pay posted by employer$141,910–$200,340 USD per year

Job Description Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of …

Added Oct 27, 2026

Save job

KLA

System Design Engineer

Milpitas, California, United States

Full time
Regular

Pay posted by employer$136,300–$231,700 per year

… devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA’s metrology and inspection …

Added Oct 15, 2026

Save job

Intel

IP RTL Senior Design Engineer

India, Bangalore

View job

Save job

Qualifications · employer excerpt

Bachelor's degree in electrical engineering, Computer Engineering, or related field.
A minimum of 8 years of experience in logic design and RTL development.
Proficiency in hardware description languages such as Verilog, System Verilog.
Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).

2 more in the full description below.

About this opportunity

Original employer description

Job Details:

Job Description:

The Role and Impact:

As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.

Key Responsibilities:

Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
Define architecture and microarchitecture features for the IP block being designed.
Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
Support SoC customers with seamless integration and verification of IP blocks.
Telemetry and debug are both observability functions rather than primary Datapath functions.
Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.

Qualifications:

Minimum Qualifications:

Bachelor's degree in electrical engineering, Computer Engineering, or related field.
A minimum of 8 years of experience in logic design and RTL development.
Proficiency in hardware description languages such as Verilog, System Verilog.
Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
Knowledge of IP block integration workflows within SoC designs.
Expertise in RAS/debug/security/telemetry.

Preferred Qualifications:

Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of professional experience encompassing complex IP logic design for high-performance applications.
Demonstrated expertise in architecture and microarchitecture definition.
Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.

Take the next step in your career and become part of Intel's world-class engineering team, shaping the future of technology with groundbreaking innovations. Apply today to make an impact.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Why this result? · Employer labels

Keywords also found in description

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.