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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Santa Clara, California, United States +1 location
… delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include …
Santa Clara, California, United States 2 postings
… work, to amplify human creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse …
Santa Clara, California, United States
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a …
Santa Clara, California, United States
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a …
Santa Clara, California, United States +1 location
Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals …
Israel, Yokneam +1 location
NVIDIA's Chip Design group is looking for best-in-class Verification Engineers to join our outstanding Silicon Engineering team, …
Israel, Tel Aviv
NVIDIA is looking for a best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the …
Bengaluru, Karnataka, India
GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform …
US-PR-AGUADILLA-110 ~ Rd 110 N Km 28.8 ~ RD110
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration …
Malaysia, Penang
The Role and Impact As a CPU Design Verification Engineer, you will play a pivotal role in ensuring the functionality and reliability of …
Office - USA - CA - Headquarters
… modules, and hardware acceleration platforms for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring-up, collaborating …
Folsom, California, United States +2 locations
Pay posted by employer$164,470–$232,190 USD per year
… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …
Austin, Texas, United States
include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in …
Bengaluru, Karnataka, India
We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll …
USA - El Segundo, CA
Pay posted by employer$119,850–$162,150
Define, develop and validate next-generation multi-ASIC architectures incorporating digital signal-processing cores for digital communication subsystems. …
Wilmington, Massachusetts, United States
Pay posted by employer$110,385–$151,808
Analog Devices, Inc. currently has a position open for a Senior MEMS Design and Simulation Engineer within the Advanced MEMS Development group under the Aerospace, …
Westford, Massachusetts, United States
… join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the …
Milpitas, California, United States
Pay posted by employer$154,900–$225,300
… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to product ion—is within our team, we’re able to think differently, experiment more, and …
Austin, Texas, United States +2 locations
Pay posted by employer$143,800–$230,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
Austin, Texas, United States +2 locations
Pay posted by employer$121,900–$195,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
