171 matching jobs for “Senior DFT Engineer”

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Nvidia

Principal Solutions Architect – Semiconductor Test

Santa Clara, California, United States

… strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead …

Added Oct 31, 2026

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Intel

Product Development/DFX Lead - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Full time
Regular

Pay posted by employer$141,910–$269,100 USD per year

… technology with the versatility demanded by modern AI workloads. Position Overview We are seeking a senior product development engineer to lead the DFT/DFX strategy for Intel's neuromorphic silicon program. This …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore)

Pune, Maharashtra, India +1 location

… expertise in high-speed optical interconnects and mastery of the complete ASIC/SoC design flow, including DFT, physical design, and verification. Furthermore, the position requires the ability to drive technical …

Added Oct 27, 2026

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Marvell Technology

Associate Vice President, Engineering – DCE Connectivity Hardware

Santa Clara, California, United States

… and into 2nm GAAFET. With deep expertise across digital design, design verification, physical design, DFT, and silicon validation, the group operates with the rigor and velocity required to deliver first-silicon …

Added Nov 10, 2026

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Nvidia

EDA Methodology Architect

Santa Clara, California, United States +1 location

… in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and …

Added Oct 31, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

… including AI/ML workloads, and next-generation data center architectures. Your Impact As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you …

Added Oct 27, 2026

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Nvidia

Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

Santa Clara, California, United States

Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team working on …

Added Oct 31, 2026

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Analog Devices

Hardware Design & Manufacture Lead

Dublin, Leinster, Ireland

… design standards, review processes, and documentation practices. Design for Manufacture at Scale Embed DFM, DFT (Design for Test), and DFA (Design for Assembly) principles into every hardware programme. Work with …

Added Nov 3, 2026

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Intel

CPU RTL Design Manager

Bengaluru, Karnataka, India

Full time
Regular

… Cross-Functional Collaboration - Partner with Architecture, Design, Validation, Physical Design, DFT, Power, Security, and Product Engineering teams. Influence technical decisions across multiple …

Added Oct 27, 2026

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Cisco Systems

Leader, Semiconductor Product Engineering

San Jose, California, United States +3 locations

Pay posted by employer$194,600–$285,700

… (HVM) Collaborate with design & test teams to establish manufacturing and test strategies, including DFT implementation, test hardware specs, and test program creation Deliver AI-Driven process transformation to …

Added Oct 27, 2026

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GE Aerospace

Test Systems Technical Lead

Cheltenham, England, United Kingdom

Full time
Regular

… system architectures and strategies are aligned to the overall product architecture. Engage SMEs and Chief Engineer’s Office as needed to resolve complex technical issues, de-risk solutions, and ensure compliance with …

Added Oct 27, 2026

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Nvidia

Principal Solutions Architect – Semiconductor Test

Santa Clara, California, United States

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About this opportunity

Original employer description

We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios.

What You'll be doing:

Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.
Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
Serve as the senior liaison between build and test engineering for DFT architecture decisions — scan, BIST, JTAG, boundary scan, and embedded compression.
Influence SoC and IP build reviews to ensure testability, observability, and debug-ability
Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.
Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.

What we need to see:

15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
Strong background in DFT architectures — scan compression, MBIST, LBIST, JTAG, and related methodologies.
Experience with mixed-signal, RF, or high-speed I/O test is highly valued.
Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
Proven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.
MSEE, MSCE, MSCS, or related field (or equivalent experience).

Ways to stand out from the crowd

Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
Knowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).
Exposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).
Prior engagement with SEMI standards committees or ATE vendor co-development programs.
Ph.D or equivalent experience in related field

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most thoughtful and dedicated people in the world working for us. Due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 216,000 USD – 345,000 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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